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author | Gabe Black <gblack@eecs.umich.edu> | 2007-04-14 17:13:18 +0000 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-04-14 17:13:18 +0000 |
commit | c3081d9c1c36e1a08c173048783d191fa19463de (patch) | |
tree | f2717bd70d64af1e6ef54ff73e3cbee7984f4b31 /src/cpu/o3/sparc | |
parent | 5a3dcc172a9fd661330909815b163eb6f4d6a2d8 (diff) | |
download | gem5-c3081d9c1c36e1a08c173048783d191fa19463de.tar.xz |
Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
--HG--
extra : convert_revision : 8b9c603616bcad254417a7a3fa3edfb4c8728719
Diffstat (limited to 'src/cpu/o3/sparc')
-rw-r--r-- | src/cpu/o3/sparc/dyn_inst.hh | 10 | ||||
-rw-r--r-- | src/cpu/o3/sparc/dyn_inst_impl.hh | 17 |
2 files changed, 23 insertions, 4 deletions
diff --git a/src/cpu/o3/sparc/dyn_inst.hh b/src/cpu/o3/sparc/dyn_inst.hh index 72242b161..a7ab6cd79 100644 --- a/src/cpu/o3/sparc/dyn_inst.hh +++ b/src/cpu/o3/sparc/dyn_inst.hh @@ -56,8 +56,14 @@ class SparcDynInst : public BaseDynInst<Impl> public: /** BaseDynInst constructor given a binary instruction. */ - SparcDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, - Addr Pred_PC, Addr Pred_NPC, InstSeqNum seq_num, O3CPU *cpu); + SparcDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, + Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, + InstSeqNum seq_num, O3CPU *cpu); + + /** BaseDynInst constructor given a binary instruction. */ + SparcDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, + Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, + InstSeqNum seq_num, O3CPU *cpu); /** BaseDynInst constructor given a static inst pointer. */ SparcDynInst(StaticInstPtr &_staticInst); diff --git a/src/cpu/o3/sparc/dyn_inst_impl.hh b/src/cpu/o3/sparc/dyn_inst_impl.hh index c4d30b6f4..6bfe97717 100644 --- a/src/cpu/o3/sparc/dyn_inst_impl.hh +++ b/src/cpu/o3/sparc/dyn_inst_impl.hh @@ -31,10 +31,23 @@ #include "cpu/o3/sparc/dyn_inst.hh" template <class Impl> +SparcDynInst<Impl>::SparcDynInst(StaticInstPtr staticInst, + Addr PC, Addr NPC, Addr microPC, + Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, + InstSeqNum seq_num, O3CPU *cpu) + : BaseDynInst<Impl>(staticInst, PC, NPC, microPC, + Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) +{ + initVars(); +} + +template <class Impl> SparcDynInst<Impl>::SparcDynInst(TheISA::ExtMachInst inst, - Addr PC, Addr NPC, Addr Pred_PC, Addr Pred_NPC, + Addr PC, Addr NPC, Addr microPC, + Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC, InstSeqNum seq_num, O3CPU *cpu) - : BaseDynInst<Impl>(inst, PC, NPC, Pred_PC, Pred_NPC, seq_num, cpu) + : BaseDynInst<Impl>(inst, PC, NPC, microPC, + Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu) { initVars(); } |