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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-02-16 03:33:28 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-02-16 03:33:28 -0500 |
| commit | d0e1b8a19c6d58a49e5288938e9b12f3f10b9f51 (patch) | |
| tree | f990864e7fb9ffaf11e3895e8337737941390aa2 /src/cpu/o3/thread_context.hh | |
| parent | 07ce60bdfa57eedf00f533704b5a2da3fa01b553 (diff) | |
| download | gem5-d0e1b8a19c6d58a49e5288938e9b12f3f10b9f51.tar.xz | |
arch: Make readMiscRegNoEffect const throughout
Finally took the plunge and made this apply to all ISAs, not just ARM.
Diffstat (limited to 'src/cpu/o3/thread_context.hh')
| -rwxr-xr-x | src/cpu/o3/thread_context.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 952d365bf..87d87900c 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -228,7 +228,7 @@ class O3ThreadContext : public ThreadContext { return cpu->microPC(thread->threadId()); } /** Reads a miscellaneous register. */ - virtual MiscReg readMiscRegNoEffect(int misc_reg) + virtual MiscReg readMiscRegNoEffect(int misc_reg) const { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } /** Reads a misc. register, including any side-effects the |