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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
| commit | 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (patch) | |
| tree | 0868fb00a7546d90971bc18acd4f7b0bbce558c0 /src/cpu/o3/thread_context.hh | |
| parent | 3e2cad8370d99f45ecf4d922d3ac8213e0d72644 (diff) | |
| download | gem5-32daf6fc3fd34af0023ae74c2a1f8dd597f87242.tar.xz | |
Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
Diffstat (limited to 'src/cpu/o3/thread_context.hh')
| -rwxr-xr-x | src/cpu/o3/thread_context.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index b10305d5d..a3f1ce58f 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -226,6 +226,9 @@ class O3ThreadContext : public ThreadContext * write might have as defined by the architecture. */ virtual void setMiscReg(int misc_reg, const MiscReg &val); + virtual int flattenIntIndex(int reg); + virtual int flattenFloatIndex(int reg); + /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. virtual unsigned readStCondFailures() |