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| author | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2018-10-16 16:04:08 +0100 |
|---|---|---|
| committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-01-30 16:57:54 +0000 |
| commit | 25474167e5b247d1b91fbf802c5b396a63ae705e (patch) | |
| tree | b509597b23d792734f55c33b8125eebfbd9cd3a5 /src/cpu/o3/thread_context.hh | |
| parent | c6f5db8743f19b02a38146d9cf2a829883387008 (diff) | |
| download | gem5-25474167e5b247d1b91fbf802c5b396a63ae705e.tar.xz | |
arch,cpu: Add vector predicate registers
Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.
Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/o3/thread_context.hh')
| -rw-r--r-- | src/cpu/o3/thread_context.hh | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index c74936469..7858f5a0a 100644 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012, 2016 ARM Limited + * Copyright (c) 2011-2012, 2016-2018 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -263,6 +263,14 @@ class O3ThreadContext : public ThreadContext return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex()); } + virtual const VecPredRegContainer& readVecPredReg(const RegId& id) const { + return readVecPredRegFlat(flattenRegId(id).index()); + } + + virtual VecPredRegContainer& getWritableVecPredReg(const RegId& id) { + return getWritableVecPredRegFlat(flattenRegId(id).index()); + } + virtual CCReg readCCReg(int reg_idx) { return readCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index()); @@ -295,6 +303,13 @@ class O3ThreadContext : public ThreadContext } virtual void + setVecPredReg(const RegId& reg, + const VecPredRegContainer& val) + { + setVecPredRegFlat(flattenRegId(reg).index(), val); + } + + virtual void setCCReg(int reg_idx, CCReg val) { setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); @@ -403,6 +418,12 @@ class O3ThreadContext : public ThreadContext virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx, const VecElem& val); + virtual const VecPredRegContainer& readVecPredRegFlat(int idx) + const override; + virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) override; + virtual void setVecPredRegFlat(int idx, + const VecPredRegContainer& val) override; + virtual CCReg readCCRegFlat(int idx); virtual void setCCRegFlat(int idx, CCReg val); }; |