diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 16:44:45 -0500 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 16:44:45 -0500 |
commit | 2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 (patch) | |
tree | 736bc7ea34184fb103fd836e67672521193602a7 /src/cpu/o3/thread_context_impl.hh | |
parent | f3ba6d20f6070c30418866e627e2418f39b433dd (diff) | |
download | gem5-2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0.tar.xz |
Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
Diffstat (limited to 'src/cpu/o3/thread_context_impl.hh')
-rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 2bc194d53..81750ada7 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -439,33 +439,28 @@ O3ThreadContext<Impl>::setNextPC(uint64_t val) } template <class Impl> -Fault +void O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) { - Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid()); + cpu->setMiscReg(misc_reg, val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { cpu->squashFromTC(thread->readTid()); } - - return ret_fault; } template <class Impl> -Fault +void O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, - thread->readTid()); + cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { cpu->squashFromTC(thread->readTid()); } - - return ret_fault; } #if !FULL_SYSTEM |