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author | Gabe Black <gblack@eecs.umich.edu> | 2007-09-19 18:26:42 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-09-19 18:26:42 -0700 |
commit | f3f3747431e001dc6c80da5b6489516b610c22d6 (patch) | |
tree | 24fcbc928df1619a82dbfd9ffa6d6f6809f509f6 /src/cpu/o3/thread_context_impl.hh | |
parent | a54ae9f92b6000e8aaf5e056deaead8725c25a74 (diff) | |
download | gem5-f3f3747431e001dc6c80da5b6489516b610c22d6.tar.xz |
X86: Put in the foundation for x87 stack based fp registers.
--HG--
extra : convert_revision : 940f92efd4a9dc59106e991cc6d9836861ab69de
Diffstat (limited to 'src/cpu/o3/thread_context_impl.hh')
-rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index a145e046e..efbbc2329 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -314,6 +314,7 @@ template <class Impl> TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); switch(width) { case 32: return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); @@ -329,6 +330,7 @@ template <class Impl> TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); } @@ -337,6 +339,7 @@ TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) { DPRINTF(Fault, "Reading floatint register through the TC!\n"); + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); } @@ -344,6 +347,7 @@ template <class Impl> TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); } @@ -364,6 +368,7 @@ template <class Impl> void O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); switch(width) { case 32: cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); @@ -383,6 +388,7 @@ template <class Impl> void O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); if (!thread->trapPending && !thread->inSyscall) { @@ -396,6 +402,7 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) { DPRINTF(Fault, "Setting floatint register through the TC!\n"); + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); // Squash if we're not already in a state update mode. @@ -408,6 +415,7 @@ template <class Impl> void O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); // Squash if we're not already in a state update mode. |