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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:39 -0400 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:39 -0400 |
| commit | 4f13f676aa71efaaae2fcd2587cf032a1d70f774 (patch) | |
| tree | 1a8dec232d4bd77df2e773e824510959c643d091 /src/cpu/o3/thread_context_impl.hh | |
| parent | 283935a6f0a17afe4574cc3c50c043515c866dfa (diff) | |
| download | gem5-4f13f676aa71efaaae2fcd2587cf032a1d70f774.tar.xz | |
cpu: Fix cache blocked load behavior in o3 cpu
This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than
flushing the entire pipeline, this patch replays loads once the cache becomes
unblocked.
Additionally, deferred memory instructions (loads which had conflicting stores),
when replayed would not respect the number of functional units (only respected
issue width). This patch also corrects that.
Improvements over 20% have been observed on a microbenchmark designed to
exercise this behavior.
Diffstat (limited to 'src/cpu/o3/thread_context_impl.hh')
0 files changed, 0 insertions, 0 deletions