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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-16 11:35:40 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-16 11:35:40 -0500 |
| commit | 9d0ca61b7e357ca5e83f97f8cb8f4f1037cc3eb5 (patch) | |
| tree | 50e7a435de1e0f5638eba9b1b030e79daaf1aee0 /src/cpu/o3/thread_context_impl.hh | |
| parent | 4da37bcd1bc2c42ce5f297a58b4b4bffa4e8cd4f (diff) | |
| parent | f4f00c5ae98c069f79a8b56ed93284daf7532c7e (diff) | |
| download | gem5-9d0ca61b7e357ca5e83f97f8cb8f4f1037cc3eb5.tar.xz | |
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/isa_parser.py:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/cpu/o3/iew_impl.hh:
Hand Merge
--HG--
extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47
Diffstat (limited to 'src/cpu/o3/thread_context_impl.hh')
| -rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index afebf294f..af98fa1f5 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -29,6 +29,7 @@ * Korey Sewell */ +#include "arch/regfile.hh" #include "cpu/o3/thread_context.hh" #include "cpu/quiesce_event.hh" @@ -305,6 +306,7 @@ template <class Impl> uint64_t O3ThreadContext<Impl>::readIntReg(int reg_idx) { + reg_idx = TheISA::flattenIntIndex(this, reg_idx); return cpu->readArchIntReg(reg_idx, thread->readTid()); } @@ -349,6 +351,7 @@ template <class Impl> void O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) { + reg_idx = TheISA::flattenIntIndex(this, reg_idx); cpu->setArchIntReg(reg_idx, val, thread->readTid()); // Squash if we're not already in a state update mode. |