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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
commit | aafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch) | |
tree | d40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/cpu/o3/thread_context_impl.hh | |
parent | 608641e23c7f2288810c3f23a1a63790b664f2ab (diff) | |
download | gem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz |
revert 5af8f40d8f2c
Diffstat (limited to 'src/cpu/o3/thread_context_impl.hh')
-rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index ecdd9ebb9..e6a3d5083 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -216,13 +216,6 @@ O3ThreadContext<Impl>::readCCRegFlat(int reg_idx) } template <class Impl> -const TheISA::VectorReg & -O3ThreadContext<Impl>::readVectorRegFlat(int reg_idx) -{ - return cpu->readArchVectorReg(reg_idx, thread->threadId()); -} - -template <class Impl> void O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val) { @@ -260,15 +253,6 @@ O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val) template <class Impl> void -O3ThreadContext<Impl>::setVectorRegFlat(int reg_idx, - const TheISA::VectorReg &val) -{ - cpu->setArchVectorReg(reg_idx, val, thread->threadId()); - conditionalSquash(); -} - -template <class Impl> -void O3ThreadContext<Impl>::pcState(const TheISA::PCState &val) { cpu->pcState(val, thread->threadId()); @@ -308,13 +292,6 @@ O3ThreadContext<Impl>::flattenCCIndex(int reg) template <class Impl> int -O3ThreadContext<Impl>::flattenVectorIndex(int reg) -{ - return cpu->isa[thread->threadId()]->flattenVectorIndex(reg); -} - -template <class Impl> -int O3ThreadContext<Impl>::flattenMiscIndex(int reg) { return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); |