cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.

1 files changed, 23 insertions, 0 deletions

diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index e6a3d5083..ecdd9ebb9 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -216,6 +216,13 @@ O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
 }
 
 template <class Impl>
+const TheISA::VectorReg &
+O3ThreadContext<Impl>::readVectorRegFlat(int reg_idx)
+{
+    return cpu->readArchVectorReg(reg_idx, thread->threadId());
+}
+
+template <class Impl>
 void
 O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
 {
@@ -253,6 +260,15 @@ O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
 
 template <class Impl>
 void
+O3ThreadContext<Impl>::setVectorRegFlat(int reg_idx,
+                                        const TheISA::VectorReg &val)
+{
+    cpu->setArchVectorReg(reg_idx, val, thread->threadId());
+    conditionalSquash();
+}
+
+template <class Impl>
+void
 O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
 {
     cpu->pcState(val, thread->threadId());
@@ -292,6 +308,13 @@ O3ThreadContext<Impl>::flattenCCIndex(int reg)
 
 template <class Impl>
 int
+O3ThreadContext<Impl>::flattenVectorIndex(int reg)
+{
+    return cpu->isa[thread->threadId()]->flattenVectorIndex(reg);
+}
+
+template <class Impl>
+int
 O3ThreadContext<Impl>::flattenMiscIndex(int reg)
 {
     return cpu->isa[thread->threadId()]->flattenMiscIndex(reg);