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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:30 -0600 |
| commit | 7d0344704a9ecc566d82ad43ec44b4becbaf4d77 (patch) | |
| tree | 4281e9fe0ff9480698ed697027e411da73e78d47 /src/cpu/o3/thread_context_impl.hh | |
| parent | 3436de0c2ad467c65066e48969a7c12bdbbb3d26 (diff) | |
| download | gem5-7d0344704a9ecc566d82ad43ec44b4becbaf4d77.tar.xz | |
arch, cpu: Add support for flattening misc register indexes.
With ARMv8 support the same misc register id results in accessing different
registers depending on the current mode of the processor. This patch adds
the same orthogonality to the misc register file as the others (int, float, cc).
For all the othre ISAs this is currently a null-implementation.
Additionally, a system variable is added to all the ISA objects.
Diffstat (limited to 'src/cpu/o3/thread_context_impl.hh')
| -rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index c818260f4..43e903135 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -292,6 +292,13 @@ O3ThreadContext<Impl>::flattenCCIndex(int reg) } template <class Impl> +int +O3ThreadContext<Impl>::flattenMiscIndex(int reg) +{ + return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); +} + +template <class Impl> void O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) { |