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| author | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-01-31 07:46:03 -0800 |
|---|---|---|
| committer | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-01-31 07:46:03 -0800 |
| commit | af6aaf258171027af8d3cf0ef86dddff501a3ccb (patch) | |
| tree | 3473845b7217b48dcf43460f0a90ca655a7018ed /src/cpu/o3/thread_context_impl.hh | |
| parent | ade53def9252a36a39b2c4bd61196355906f0505 (diff) | |
| download | gem5-af6aaf258171027af8d3cf0ef86dddff501a3ccb.tar.xz | |
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU. These changes have only been tested with the ARM ISA. Other
ISAs potentially require modification.
Diffstat (limited to 'src/cpu/o3/thread_context_impl.hh')
| -rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 4c2fee22d..5a412c161 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010-2011 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -43,6 +43,7 @@ #include "arch/registers.hh" #include "config/the_isa.hh" +#include "config/use_checker.hh" #include "cpu/o3/thread_context.hh" #include "cpu/quiesce_event.hh" #include "debug/O3CPU.hh" @@ -323,6 +324,20 @@ O3ThreadContext<Impl>::pcState(const TheISA::PCState &val) } } +#if USE_CHECKER +template <class Impl> +void +O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val) +{ + cpu->pcState(val, thread->threadId()); + + // Squash if we're not already in a state update mode. + if (!thread->trapPending && !thread->inSyscall) { + cpu->squashFromTC(thread->threadId()); + } +} +#endif + template <class Impl> int O3ThreadContext<Impl>::flattenIntIndex(int reg) |