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authorRekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com>2017-04-05 13:24:23 -0500
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-07-05 14:43:49 +0000
commit166da650a3c864b31193ade893ed99e547c67644 (patch)
tree84236bf28007885e864e885fab8e715e332affa6 /src/cpu/o3
parent00da08902918da13fccc3f2266b7b2f5d0080708 (diff)
downloadgem5-166da650a3c864b31193ade893ed99e547c67644.tar.xz
arch: ISA parser additions of vector registers
Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/commit.hh2
-rw-r--r--src/cpu/o3/commit_impl.hh10
-rw-r--r--src/cpu/o3/inst_queue.hh6
-rw-r--r--src/cpu/o3/inst_queue_impl.hh50
4 files changed, 59 insertions, 9 deletions
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 3cce7f69c..5977f94f3 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -517,6 +517,8 @@ class DefaultCommit
Stats::Vector statComMembars;
/** Total number of committed branches. */
Stats::Vector statComBranches;
+ /** Total number of vector instructions */
+ Stats::Vector statComVector;
/** Total number of floating point instructions */
Stats::Vector statComFloating;
/** Total number of integer instructions */
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index ea77f18fb..aba2696c2 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -260,6 +260,13 @@ DefaultCommit<Impl>::regStats()
.flags(total)
;
+ statComVector
+ .init(cpu->numThreads)
+ .name(name() + ".vec_insts")
+ .desc("Number of committed Vector instructions.")
+ .flags(total)
+ ;
+
statComInteger
.init(cpu->numThreads)
.name(name()+".int_insts")
@@ -1404,6 +1411,9 @@ DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
// Floating Point Instruction
if (inst->isFloating())
statComFloating[tid]++;
+ // Vector Instruction
+ if (inst->isVector())
+ statComVector[tid]++;
// Function Calls
if (inst->isCall())
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 23d8d416c..64f8aa1be 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -543,10 +543,14 @@ class InstructionQueue
Stats::Scalar intInstQueueWakeupAccesses;
Stats::Scalar fpInstQueueReads;
Stats::Scalar fpInstQueueWrites;
- Stats::Scalar fpInstQueueWakeupQccesses;
+ Stats::Scalar fpInstQueueWakeupAccesses;
+ Stats::Scalar vecInstQueueReads;
+ Stats::Scalar vecInstQueueWrites;
+ Stats::Scalar vecInstQueueWakeupAccesses;
Stats::Scalar intAluAccesses;
Stats::Scalar fpAluAccesses;
+ Stats::Scalar vecAluAccesses;
};
#endif //__CPU_O3_INST_QUEUE_HH__
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 2b113ae04..3da72fd86 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -364,7 +364,7 @@ InstructionQueue<Impl>::regStats()
.desc("Number of floating instruction queue writes")
.flags(total);
- fpInstQueueWakeupQccesses
+ fpInstQueueWakeupAccesses
.name(name() + ".fp_inst_queue_wakeup_accesses")
.desc("Number of floating instruction queue wakeup accesses")
.flags(total);
@@ -567,7 +567,13 @@ template <class Impl>
void
InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
{
- new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
+ if (new_inst->isFloating()) {
+ fpInstQueueWrites++;
+ } else if (new_inst->isVector()) {
+ vecInstQueueWrites++;
+ } else {
+ intInstQueueWrites++;
+ }
// Make sure the instruction is valid
assert(new_inst);
@@ -609,7 +615,13 @@ InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
{
// @todo: Clean up this code; can do it by setting inst as unable
// to issue, then calling normal insert on the inst.
- new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
+ if (new_inst->isFloating()) {
+ fpInstQueueWrites++;
+ } else if (new_inst->isVector()) {
+ vecInstQueueWrites++;
+ } else {
+ intInstQueueWrites++;
+ }
assert(new_inst);
@@ -660,8 +672,10 @@ InstructionQueue<Impl>::getInstToExecute()
assert(!instsToExecute.empty());
DynInstPtr inst = instsToExecute.front();
instsToExecute.pop_front();
- if (inst->isFloating()){
+ if (inst->isFloating()) {
fpInstQueueReads++;
+ } else if (inst->isVector()) {
+ vecInstQueueReads++;
} else {
intInstQueueReads++;
}
@@ -783,7 +797,13 @@ InstructionQueue<Impl>::scheduleReadyInsts()
DynInstPtr issuing_inst = readyInsts[op_class].top();
- issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++;
+ if (issuing_inst->isFloating()) {
+ fpInstQueueReads++;
+ } else if (issuing_inst->isVector()) {
+ vecInstQueueReads++;
+ } else {
+ intInstQueueReads++;
+ }
assert(issuing_inst->seqNum == (*order_it).oldestInst);
@@ -810,7 +830,13 @@ InstructionQueue<Impl>::scheduleReadyInsts()
if (op_class != No_OpClass) {
idx = fuPool->getUnit(op_class);
- issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
+ if (issuing_inst->isFloating()) {
+ fpAluAccesses++;
+ } else if (issuing_inst->isVector()) {
+ vecAluAccesses++;
+ } else {
+ intAluAccesses++;
+ }
if (idx > FUPool::NoFreeFU) {
op_latency = fuPool->getOpLatency(op_class);
}
@@ -955,7 +981,9 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
// The instruction queue here takes care of both floating and int ops
if (completed_inst->isFloating()) {
- fpInstQueueWakeupQccesses++;
+ fpInstQueueWakeupAccesses++;
+ } else if (completed_inst->isVector()) {
+ vecInstQueueWakeupAccesses++;
} else {
intInstQueueWakeupAccesses++;
}
@@ -1189,7 +1217,13 @@ InstructionQueue<Impl>::doSquash(ThreadID tid)
(*squash_it)->seqNum > squashedSeqNum[tid]) {
DynInstPtr squashed_inst = (*squash_it);
- squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
+ if (squashed_inst->isFloating()) {
+ fpInstQueueWrites++;
+ } else if (squashed_inst->isVector()) {
+ vecInstQueueWrites++;
+ } else {
+ intInstQueueWrites++;
+ }
// Only handle the instruction if it actually is in the IQ and
// hasn't already been squashed in the IQ.