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authorPaul Rosenfeld <dramninjas@gmail.com>2014-03-12 07:03:22 -0500
committerPaul Rosenfeld <dramninjas@gmail.com>2014-03-12 07:03:22 -0500
commit32bf74cb8ee4c9293636041c05d93fbfd01087da (patch)
treea8f219af38c3986aee56ffadae8ecdb0dd618cf9 /src/cpu/o3
parent62fe81e9c1ab09f1b401231f58d9c34008c7b558 (diff)
downloadgem5-32bf74cb8ee4c9293636041c05d93fbfd01087da.tar.xz
alpha: Small removal of dead comments/code from alpha ISA
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/dyn_inst.hh7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 5477f46d6..76bd8b291 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -54,13 +54,6 @@
class Packet;
-/**
- * Mostly implementation & ISA specific AlphaDynInst. As with most
- * other classes in the new CPU model, it is templated on the Impl to
- * allow for passing in of all types, such as the CPU type and the ISA
- * type. The AlphaDynInst serves as the primary interface to the CPU
- * for instructions that are executing.
- */
template <class Impl>
class BaseO3DynInst : public BaseDynInst<Impl>
{