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authorGabe Black <gblack@eecs.umich.edu>2011-08-09 03:37:43 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-08-09 03:37:43 -0700
commit3989f41261b9d13f336a37cb6717f9fdb5a71bb1 (patch)
tree8dcde9bcd1448e157b7bcff0dbe9c889faec1b3f /src/cpu/o3
parent821dfc12892ee841916d9aab411f2db7937ba7c4 (diff)
downloadgem5-3989f41261b9d13f336a37cb6717f9fdb5a71bb1.tar.xz
O3: When waiting to handle an interrupt, let everything drain out.
Before this change, the commit stage would wait until the ROB and store queue were empty before recognizing an interrupt. The fetch stage would stop generating instructions at an appropriate point, so commit would then wait until a valid time to interrupt the instruction stream. Instructions might be in flight after fetch but not the in the ROB or store queue (in rename, for instance), so this change makes commit wait until all in flight instructions are finished.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/commit_impl.hh6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index f579305dc..c0946c16f 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -714,9 +714,9 @@ DefaultCommit<Impl>::handleInterrupt()
return;
}
- // Wait until the ROB is empty and all stores have drained in
- // order to enter the interrupt.
- if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
+ // Wait until all in flight instructions are finished before enterring
+ // the interrupt.
+ if (cpu->instList.empty()) {
// Squash or record that I need to squash this cycle if
// an interrupt needed to be handled.
DPRINTF(Commit, "Interrupt detected.\n");