cpu: add consistent guarding to *_impl.hh files.

12 files changed, 57 insertions, 0 deletions

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 2c1c9fef2..becdfd06c 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -40,6 +40,8 @@
  * Authors: Kevin Lim
  *          Korey Sewell
  */
+#ifndef __CPU_O3_COMMIT_IMPL_HH__
+#define __CPU_O3_COMMIT_IMPL_HH__
 
 #include <algorithm>
 #include <set>
@@ -1540,3 +1542,5 @@ DefaultCommit<Impl>::oldestReady()
         return InvalidThreadID;
     }
 }
+
+#endif//__CPU_O3_COMMIT_IMPL_HH__
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 9ab672931..c78e7f211 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -40,6 +40,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_O3_DECODE_IMPL_HH__
+#define __CPU_O3_DECODE_IMPL_HH__
+
 #include "arch/types.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
@@ -767,3 +770,5 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
         wroteToTimeBuffer = true;
     }
 }
+
+#endif//__CPU_O3_DECODE_IMPL_HH__
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 347d30324..4e1492077 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -40,6 +40,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_O3_DYN_INST_IMPL_HH__
+#define __CPU_O3_DYN_INST_IMPL_HH__
+
 #include "base/cp_annotate.hh"
 #include "cpu/o3/dyn_inst.hh"
 #include "sim/full_system.hh"
@@ -255,3 +258,4 @@ BaseO3DynInst<Impl>::syscall(int64_t callnum)
     }
 }
 
+#endif//__CPU_O3_DYN_INST_IMPL_HH__
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index f6e46cc26..d97c5ba36 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -41,6 +41,9 @@
  *          Korey Sewell
  */
 
+#ifndef __CPU_O3_FETCH_IMPL_HH__
+#define __CPU_O3_FETCH_IMPL_HH__
+
 #include <algorithm>
 #include <cstring>
 #include <list>
@@ -1631,3 +1634,5 @@ DefaultFetch<Impl>::profileStall(ThreadID tid) {
              tid, fetchStatus[tid]);
     }
 }
+
+#endif//__CPU_O3_FETCH_IMPL_HH__
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 947318d60..6c5c57fb7 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -40,6 +40,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__
+#define __CPU_O3_IEW_IMPL_IMPL_HH__
+
 // @todo: Fix the instantaneous communication among all the stages within
 // iew.  There's a clear delay between issue and execute, yet backwards
 // communication happens simultaneously.
@@ -1671,3 +1674,5 @@ DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
         }
     }
 }
+
+#endif//__CPU_O3_IEW_IMPL_IMPL_HH__
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 1c86b7c89..f0b682602 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -42,6 +42,9 @@
  *          Korey Sewell
  */
 
+#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__
+#define __CPU_O3_INST_QUEUE_IMPL_HH__
+
 #include <limits>
 #include <vector>
 
@@ -1508,3 +1511,5 @@ InstructionQueue<Impl>::dumpInsts()
         ++num;
     }
 }
+
+#endif//__CPU_O3_INST_QUEUE_IMPL_HH__
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 70db92714..7e89968a8 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -40,6 +40,9 @@
  * Authors: Korey Sewell
  */
 
+#ifndef __CPU_O3_LSQ_IMPL_HH__
+#define __CPU_O3_LSQ_IMPL_HH__
+
 #include <algorithm>
 #include <list>
 #include <string>
@@ -658,3 +661,5 @@ LSQ<Impl>::dumpInsts() const
         thread[tid].dumpInsts();
     }
 }
+
+#endif//__CPU_O3_LSQ_IMPL_HH__
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 44b8e9041..77b67ac69 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -42,6 +42,9 @@
  *          Korey Sewell
  */
 
+#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__
+#define __CPU_O3_LSQ_UNIT_IMPL_HH__
+
 #include "arch/generic/debugfaults.hh"
 #include "arch/locked_mem.hh"
 #include "base/str.hh"
@@ -1289,3 +1292,5 @@ LSQUnit<Impl>::dumpInsts() const
 
     cprintf("\n");
 }
+
+#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh
index 7fbea0216..009ae2b48 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -40,6 +40,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_O3_MEM_DEP_UNIT_IMPL_HH__
+#define __CPU_O3_MEM_DEP_UNIT_IMPL_HH__
+
 #include <map>
 
 #include "cpu/o3/inst_queue.hh"
@@ -594,3 +597,5 @@ MemDepUnit<MemDepPred, Impl>::dumpLists()
     cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
 #endif
 }
+
+#endif//__CPU_O3_MEM_DEP_UNIT_IMPL_HH__
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index db7189371..242d5a4e3 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -42,6 +42,9 @@
  *          Korey Sewell
  */
 
+#ifndef __CPU_O3_RENAME_IMPL_HH__
+#define __CPU_O3_RENAME_IMPL_HH__
+
 #include <list>
 
 #include "arch/isa_traits.hh"
@@ -1383,3 +1386,5 @@ DefaultRename<Impl>::dumpHistory()
         }
     }
 }
+
+#endif//__CPU_O3_RENAME_IMPL_HH__
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index b33221f15..c8ceb2909 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -41,6 +41,9 @@
  *          Korey Sewell
  */
 
+#ifndef __CPU_O3_ROB_IMPL_HH__
+#define __CPU_O3_ROB_IMPL_HH__
+
 #include <list>
 
 #include "cpu/o3/rob.hh"
@@ -560,3 +563,5 @@ ROB<Impl>::findInst(ThreadID tid, InstSeqNum squash_inst)
     }
     return NULL;
 }
+
+#endif//__CPU_O3_ROB_IMPL_HH__
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 006d325fc..c818260f4 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -42,6 +42,9 @@
  *          Korey Sewell
  */
 
+#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
+#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
+
 #include "arch/kernel_stats.hh"
 #include "arch/registers.hh"
 #include "config/the_isa.hh"
@@ -297,6 +300,7 @@ O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
     conditionalSquash();
 }
 
+#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
 template <class Impl>
 void
 O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)