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authorGabe Black <gblack@eecs.umich.edu>2010-10-31 00:07:20 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-10-31 00:07:20 -0700
commit6f4bd2c1da0dc7783da87c4877a41332901199b2 (patch)
tree99f2898e2b659338fd0b01d86eb9a4f8d981e21a /src/cpu/o3
parent373154a25afb1bed946e5a2a7cfd411e4bd7fad6 (diff)
downloadgem5-6f4bd2c1da0dc7783da87c4877a41332901199b2.tar.xz
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/bpred_unit.hh33
-rw-r--r--src/cpu/o3/bpred_unit_impl.hh103
-rw-r--r--src/cpu/o3/comm.hh13
-rw-r--r--src/cpu/o3/commit.hh55
-rw-r--r--src/cpu/o3/commit_impl.hh86
-rw-r--r--src/cpu/o3/cpu.cc83
-rw-r--r--src/cpu/o3/cpu.hh33
-rw-r--r--src/cpu/o3/decode_impl.hh51
-rw-r--r--src/cpu/o3/dep_graph.hh8
-rw-r--r--src/cpu/o3/dyn_inst.hh12
-rw-r--r--src/cpu/o3/dyn_inst_impl.hh32
-rw-r--r--src/cpu/o3/fetch.hh20
-rw-r--r--src/cpu/o3/fetch_impl.hh178
-rw-r--r--src/cpu/o3/iew_impl.hh94
-rw-r--r--src/cpu/o3/inst_queue_impl.hh49
-rw-r--r--src/cpu/o3/lsq_unit.hh8
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh44
-rw-r--r--src/cpu/o3/mem_dep_unit_impl.hh52
-rw-r--r--src/cpu/o3/rename_impl.hh23
-rw-r--r--src/cpu/o3/rob_impl.hh8
-rwxr-xr-xsrc/cpu/o3/thread_context.hh42
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh46
22 files changed, 400 insertions, 673 deletions
diff --git a/src/cpu/o3/bpred_unit.hh b/src/cpu/o3/bpred_unit.hh
index f199bdd75..58b1147c9 100644
--- a/src/cpu/o3/bpred_unit.hh
+++ b/src/cpu/o3/bpred_unit.hh
@@ -88,7 +88,7 @@ class BPredUnit
* @param tid The thread id.
* @return Returns if the branch is taken or not.
*/
- bool predict(DynInstPtr &inst, Addr &PC, ThreadID tid);
+ bool predict(DynInstPtr &inst, TheISA::PCState &pc, ThreadID tid);
// @todo: Rename this function.
void BPUncond(void * &bp_history);
@@ -118,7 +118,8 @@ class BPredUnit
* @param actually_taken The correct branch direction.
* @param tid The thread id.
*/
- void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
+ void squash(const InstSeqNum &squashed_sn,
+ const TheISA::PCState &corr_target,
bool actually_taken, ThreadID tid);
/**
@@ -134,23 +135,23 @@ class BPredUnit
* has the branch predictor state associated with the lookup.
* @return Whether the branch is taken or not taken.
*/
- bool BPLookup(Addr &inst_PC, void * &bp_history);
+ bool BPLookup(Addr instPC, void * &bp_history);
/**
* Looks up a given PC in the BTB to see if a matching entry exists.
* @param inst_PC The PC to look up.
* @return Whether the BTB contains the given PC.
*/
- bool BTBValid(Addr &inst_PC)
- { return BTB.valid(inst_PC, 0); }
+ bool BTBValid(Addr instPC)
+ { return BTB.valid(instPC, 0); }
/**
* Looks up a given PC in the BTB to get the predicted target.
* @param inst_PC The PC to look up.
* @return The address of the target of the branch.
*/
- Addr BTBLookup(Addr &inst_PC)
- { return BTB.lookup(inst_PC, 0); }
+ TheISA::PCState BTBLookup(Addr instPC)
+ { return BTB.lookup(instPC, 0); }
/**
* Updates the BP with taken/not taken information.
@@ -160,15 +161,15 @@ class BPredUnit
* associated with the branch lookup that is being updated.
* @todo Make this update flexible enough to handle a global predictor.
*/
- void BPUpdate(Addr &inst_PC, bool taken, void *bp_history);
+ void BPUpdate(Addr instPC, bool taken, void *bp_history);
/**
* Updates the BTB with the target of a branch.
* @param inst_PC The branch's PC that will be updated.
* @param target_PC The branch's target that will be added to the BTB.
*/
- void BTBUpdate(Addr &inst_PC, Addr &target_PC)
- { BTB.update(inst_PC, target_PC,0); }
+ void BTBUpdate(Addr instPC, const TheISA::PCState &target)
+ { BTB.update(instPC, target, 0); }
void dump();
@@ -178,13 +179,13 @@ class BPredUnit
* Makes a predictor history struct that contains any
* information needed to update the predictor, BTB, and RAS.
*/
- PredictorHistory(const InstSeqNum &seq_num, const Addr &inst_PC,
+ PredictorHistory(const InstSeqNum &seq_num, Addr instPC,
bool pred_taken, void *bp_history,
ThreadID _tid)
- : seqNum(seq_num), PC(inst_PC), RASTarget(0),
- RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0),
+ : seqNum(seq_num), pc(instPC), RASTarget(0), RASIndex(0),
+ tid(_tid), predTaken(pred_taken), usedRAS(0),
wasCall(0), bpHistory(bp_history)
- { }
+ {}
bool operator==(const PredictorHistory &entry) const {
return this->seqNum == entry.seqNum;
@@ -194,10 +195,10 @@ class BPredUnit
InstSeqNum seqNum;
/** The PC associated with the sequence number. */
- Addr PC;
+ Addr pc;
/** The RAS target (only valid if a return). */
- Addr RASTarget;
+ TheISA::PCState RASTarget;
/** The RAS index of the instruction (only valid if a call). */
unsigned RASIndex;
diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh
index ed3471761..14d47df9f 100644
--- a/src/cpu/o3/bpred_unit_impl.hh
+++ b/src/cpu/o3/bpred_unit_impl.hh
@@ -31,6 +31,7 @@
#include <algorithm>
#include "arch/types.hh"
+#include "arch/utility.hh"
#include "arch/isa_traits.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
@@ -144,17 +145,15 @@ BPredUnit<Impl>::takeOverFrom()
template <class Impl>
bool
-BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, ThreadID tid)
+BPredUnit<Impl>::predict(DynInstPtr &inst, TheISA::PCState &pc, ThreadID tid)
{
// See if branch predictor predicts taken.
// If so, get its target addr either from the BTB or the RAS.
// Save off record of branch stuff so the RAS can be fixed
// up once it's done.
- using TheISA::MachInst;
-
bool pred_taken = false;
- Addr target = PC;
+ TheISA::PCState target = pc;
++lookups;
@@ -168,19 +167,19 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, ThreadID tid)
} else {
++condPredicted;
- pred_taken = BPLookup(PC, bp_history);
+ pred_taken = BPLookup(pc.instAddr(), bp_history);
DPRINTF(Fetch, "BranchPred: [tid:%i]: Branch predictor predicted %i "
- "for PC %#x\n",
- tid, pred_taken, inst->readPC());
+ "for PC %s\n",
+ tid, pred_taken, inst->pcState());
}
DPRINTF(Fetch, "BranchPred: [tid:%i]: [sn:%i] Creating prediction history "
- "for PC %#x\n",
- tid, inst->seqNum, inst->readPC());
+ "for PC %s\n",
+ tid, inst->seqNum, inst->pcState());
- PredictorHistory predict_record(inst->seqNum, PC, pred_taken,
- bp_history, tid);
+ PredictorHistory predict_record(inst->seqNum, pc.instAddr(),
+ pred_taken, bp_history, tid);
// Now lookup in the BTB or RAS.
if (pred_taken) {
@@ -189,60 +188,58 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, ThreadID tid)
// If it's a function return call, then look up the address
// in the RAS.
- target = RAS[tid].top();
+ TheISA::PCState rasTop = RAS[tid].top();
+ target = TheISA::buildRetPC(pc, rasTop);
// Record the top entry of the RAS, and its index.
predict_record.usedRAS = true;
predict_record.RASIndex = RAS[tid].topIdx();
- predict_record.RASTarget = target;
+ predict_record.RASTarget = rasTop;
assert(predict_record.RASIndex < 16);
RAS[tid].pop();
- DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x is a return, "
- "RAS predicted target: %#x, RAS index: %i.\n",
- tid, inst->readPC(), target, predict_record.RASIndex);
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %s is a return, "
+ "RAS predicted target: %s, RAS index: %i.\n",
+ tid, inst->pcState(), target, predict_record.RASIndex);
} else {
++BTBLookups;
if (inst->isCall()) {
-#if ISA_HAS_DELAY_SLOT
- Addr ras_pc = PC + (2 * sizeof(MachInst)); // Next Next PC
-#else
- Addr ras_pc = PC + sizeof(MachInst); // Next PC
-#endif
- RAS[tid].push(ras_pc);
+ RAS[tid].push(pc);
// Record that it was a call so that the top RAS entry can
// be popped off if the speculation is incorrect.
predict_record.wasCall = true;
- DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x was a call"
- ", adding %#x to the RAS index: %i.\n",
- tid, inst->readPC(), ras_pc, RAS[tid].topIdx());
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %s was a "
+ "call, adding %s to the RAS index: %i.\n",
+ tid, inst->pcState(), pc, RAS[tid].topIdx());
}
- if (BTB.valid(PC, tid)) {
+ if (BTB.valid(pc.instAddr(), tid)) {
++BTBHits;
// If it's not a return, use the BTB to get the target addr.
- target = BTB.lookup(PC, tid);
+ target = BTB.lookup(pc.instAddr(), tid);
- DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x predicted"
- " target is %#x.\n",
- tid, inst->readPC(), target);
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %s predicted"
+ " target is %s.\n", tid, inst->pcState(), target);
} else {
DPRINTF(Fetch, "BranchPred: [tid:%i]: BTB doesn't have a "
"valid entry.\n",tid);
pred_taken = false;
+ TheISA::advancePC(target, inst->staticInst);
}
}
+ } else {
+ TheISA::advancePC(target, inst->staticInst);
}
- PC = target;
+ pc = target;
predHist[tid].push_front(predict_record);
@@ -262,7 +259,7 @@ BPredUnit<Impl>::update(const InstSeqNum &done_sn, ThreadID tid)
while (!predHist[tid].empty() &&
predHist[tid].back().seqNum <= done_sn) {
// Update the branch predictor with the correct results.
- BPUpdate(predHist[tid].back().PC,
+ BPUpdate(predHist[tid].back().pc,
predHist[tid].back().predTaken,
predHist[tid].back().bpHistory);
@@ -280,10 +277,8 @@ BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, ThreadID tid)
pred_hist.front().seqNum > squashed_sn) {
if (pred_hist.front().usedRAS) {
DPRINTF(Fetch, "BranchPred: [tid:%i]: Restoring top of RAS to: %i,"
- " target: %#x.\n",
- tid,
- pred_hist.front().RASIndex,
- pred_hist.front().RASTarget);
+ " target: %s.\n", tid,
+ pred_hist.front().RASIndex, pred_hist.front().RASTarget);
RAS[tid].restore(pred_hist.front().RASIndex,
pred_hist.front().RASTarget);
@@ -298,11 +293,13 @@ BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, ThreadID tid)
BPSquash(pred_hist.front().bpHistory);
DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing history for [sn:%i] "
- "PC %#x.\n", tid, pred_hist.front().seqNum, pred_hist.front().PC);
+ "PC %s.\n", tid, pred_hist.front().seqNum,
+ pred_hist.front().pc);
pred_hist.pop_front();
- DPRINTF(Fetch, "[tid:%i]: predHist.size(): %i\n", tid, predHist[tid].size());
+ DPRINTF(Fetch, "[tid:%i]: predHist.size(): %i\n",
+ tid, predHist[tid].size());
}
}
@@ -310,7 +307,7 @@ BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, ThreadID tid)
template <class Impl>
void
BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn,
- const Addr &corr_target,
+ const TheISA::PCState &corrTarget,
bool actually_taken,
ThreadID tid)
{
@@ -330,8 +327,8 @@ BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn,
++condIncorrect;
DPRINTF(Fetch, "BranchPred: [tid:%i]: Squashing from sequence number %i, "
- "setting target to %#x.\n",
- tid, squashed_sn, corr_target);
+ "setting target to %s.\n",
+ tid, squashed_sn, corrTarget);
// Squash All Branches AFTER this mispredicted branch
squash(squashed_sn, tid);
@@ -358,13 +355,13 @@ BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn,
++RASIncorrect;
}
- BPUpdate((*hist_it).PC, actually_taken,
+ BPUpdate((*hist_it).pc, actually_taken,
pred_hist.front().bpHistory);
- BTB.update((*hist_it).PC, corr_target, tid);
+ BTB.update((*hist_it).pc, corrTarget, tid);
DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing history for [sn:%i] "
- "PC %#x.\n", tid, (*hist_it).seqNum, (*hist_it).PC);
+ "PC %s.\n", tid, (*hist_it).seqNum, (*hist_it).pc);
pred_hist.erase(hist_it);
@@ -397,12 +394,12 @@ BPredUnit<Impl>::BPSquash(void *bp_history)
template <class Impl>
bool
-BPredUnit<Impl>::BPLookup(Addr &inst_PC, void * &bp_history)
+BPredUnit<Impl>::BPLookup(Addr instPC, void * &bp_history)
{
if (predictor == Local) {
- return localBP->lookup(inst_PC, bp_history);
+ return localBP->lookup(instPC, bp_history);
} else if (predictor == Tournament) {
- return tournamentBP->lookup(inst_PC, bp_history);
+ return tournamentBP->lookup(instPC, bp_history);
} else {
panic("Predictor type is unexpected value!");
}
@@ -410,12 +407,12 @@ BPredUnit<Impl>::BPLookup(Addr &inst_PC, void * &bp_history)
template <class Impl>
void
-BPredUnit<Impl>::BPUpdate(Addr &inst_PC, bool taken, void *bp_history)
+BPredUnit<Impl>::BPUpdate(Addr instPC, bool taken, void *bp_history)
{
if (predictor == Local) {
- localBP->update(inst_PC, taken, bp_history);
+ localBP->update(instPC, taken, bp_history);
} else if (predictor == Tournament) {
- tournamentBP->update(inst_PC, taken, bp_history);
+ tournamentBP->update(instPC, taken, bp_history);
} else {
panic("Predictor type is unexpected value!");
}
@@ -436,9 +433,9 @@ BPredUnit<Impl>::dump()
while (pred_hist_it != predHist[i].end()) {
cprintf("[sn:%lli], PC:%#x, tid:%i, predTaken:%i, "
"bpHistory:%#x\n",
- (*pred_hist_it).seqNum, (*pred_hist_it).PC,
- (*pred_hist_it).tid, (*pred_hist_it).predTaken,
- (*pred_hist_it).bpHistory);
+ pred_hist_it->seqNum, pred_hist_it->pc,
+ pred_hist_it->tid, pred_hist_it->predTaken,
+ pred_hist_it->bpHistory);
pred_hist_it++;
}
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index 23b836f73..c9fb3319b 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -33,6 +33,7 @@
#include <vector>
+#include "arch/types.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "sim/faults.hh"
@@ -88,9 +89,7 @@ struct DefaultIEWDefaultCommit {
bool branchMispredict[Impl::MaxThreads];
bool branchTaken[Impl::MaxThreads];
Addr mispredPC[Impl::MaxThreads];
- Addr nextPC[Impl::MaxThreads];
- Addr nextNPC[Impl::MaxThreads];
- Addr nextMicroPC[Impl::MaxThreads];
+ TheISA::PCState pc[Impl::MaxThreads];
InstSeqNum squashedSeqNum[Impl::MaxThreads];
bool includeSquashInst[Impl::MaxThreads];
@@ -120,9 +119,7 @@ struct TimeBufStruct {
bool branchMispredict;
bool branchTaken;
Addr mispredPC;
- Addr nextPC;
- Addr nextNPC;
- Addr nextMicroPC;
+ TheISA::PCState nextPC;
unsigned branchCount;
};
@@ -161,9 +158,7 @@ struct TimeBufStruct {
bool branchMispredict;
bool branchTaken;
Addr mispredPC;
- Addr nextPC;
- Addr nextNPC;
- Addr nextMicroPC;
+ TheISA::PCState pc;
// Represents the instruction that has either been retired or
// squashed. Similar to having a single bus that broadcasts the
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index d93b85984..326f3a1d3 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -277,40 +277,21 @@ class DefaultCommit
ThreadID oldestReady();
public:
- /** Returns the PC of the head instruction of the ROB.
- * @todo: Probably remove this function as it returns only thread 0.
- */
- Addr readPC() { return PC[0]; }
-
- /** Returns the PC of a specific thread. */
- Addr readPC(ThreadID tid) { return PC[tid]; }
+ /** Reads the PC of a specific thread. */
+ TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }
/** Sets the PC of a specific thread. */
- void setPC(Addr val, ThreadID tid) { PC[tid] = val; }
-
- /** Reads the micro PC of a specific thread. */
- Addr readMicroPC(ThreadID tid) { return microPC[tid]; }
-
- /** Sets the micro PC of a specific thread */
- void setMicroPC(Addr val, ThreadID tid) { microPC[tid] = val; }
-
- /** Reads the next PC of a specific thread. */
- Addr readNextPC(ThreadID tid) { return nextPC[tid]; }
-
- /** Sets the next PC of a specific thread. */
- void setNextPC(Addr val, ThreadID tid) { nextPC[tid] = val; }
+ void pcState(const TheISA::PCState &val, ThreadID tid)
+ { pc[tid] = val; }
- /** Reads the next NPC of a specific thread. */
- Addr readNextNPC(ThreadID tid) { return nextNPC[tid]; }
+ /** Returns the PC of a specific thread. */
+ Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
- /** Sets the next NPC of a specific thread. */
- void setNextNPC(Addr val, ThreadID tid) { nextNPC[tid] = val; }
+ /** Returns the next PC of a specific thread. */
+ Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
/** Reads the micro PC of a specific thread. */
- Addr readNextMicroPC(ThreadID tid) { return nextMicroPC[tid]; }
-
- /** Sets the micro PC of a specific thread */
- void setNextMicroPC(Addr val, ThreadID tid) { nextMicroPC[tid] = val; }
+ Addr microPC(ThreadID tid) { return pc[tid].microPC(); }
private:
/** Time buffer interface. */
@@ -410,24 +391,10 @@ class DefaultCommit
/** The interrupt fault. */
Fault interrupt;
- /** The commit PC of each thread. Refers to the instruction that
- * is currently being processed/committed.
- */
- Addr PC[Impl::MaxThreads];
-
- /** The commit micro PC of each thread. Refers to the instruction that
+ /** The commit PC state of each thread. Refers to the instruction that
* is currently being processed/committed.
*/
- Addr microPC[Impl::MaxThreads];
-
- /** The next PC of each thread. */
- Addr nextPC[Impl::MaxThreads];
-
- /** The next NPC of each thread. */
- Addr nextNPC[Impl::MaxThreads];
-
- /** The next micro PC of each thread. */
- Addr nextMicroPC[Impl::MaxThreads];
+ TheISA::PCState pc[Impl::MaxThreads];
/** The sequence number of the youngest valid instruction in the ROB. */
InstSeqNum youngestSeqNum[Impl::MaxThreads];
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 98c7b49c8..8d3edfb19 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -128,11 +128,7 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
committedStores[tid] = false;
trapSquash[tid] = false;
tcSquash[tid] = false;
- microPC[tid] = 0;
- nextMicroPC[tid] = 0;
- PC[tid] = 0;
- nextPC[tid] = 0;
- nextNPC[tid] = 0;
+ pc[tid].set(0);
}
#if FULL_SYSTEM
interrupt = NoFault;
@@ -513,9 +509,7 @@ DefaultCommit<Impl>::squashAll(ThreadID tid)
toIEW->commitInfo[tid].branchMispredict = false;
- toIEW->commitInfo[tid].nextPC = PC[tid];
- toIEW->commitInfo[tid].nextNPC = nextPC[tid];
- toIEW->commitInfo[tid].nextMicroPC = nextMicroPC[tid];
+ toIEW->commitInfo[tid].pc = pc[tid];
}
template <class Impl>
@@ -524,7 +518,7 @@ DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
{
squashAll(tid);
- DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
+ DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
thread[tid]->trapPending = false;
thread[tid]->inSyscall = false;
@@ -542,7 +536,7 @@ DefaultCommit<Impl>::squashFromTC(ThreadID tid)
{
squashAll(tid);
- DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
+ DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
thread[tid]->inSyscall = false;
assert(!thread[tid]->trapPending);
@@ -611,16 +605,16 @@ DefaultCommit<Impl>::tick()
DynInstPtr inst = rob->readHeadInst(tid);
- DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
+ DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
" ROB and ready to commit\n",
- tid, inst->seqNum, inst->readPC());
+ tid, inst->seqNum, inst->pcState());
} else if (!rob->isEmpty(tid)) {
DynInstPtr inst = rob->readHeadInst(tid);
DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
- "%#x is head of ROB and not ready\n",
- tid, inst->seqNum, inst->readPC());
+ "%s is head of ROB and not ready\n",
+ tid, inst->seqNum, inst->pcState());
}
DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
@@ -738,7 +732,7 @@ DefaultCommit<Impl>::commit()
DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
tid,
- fromIEW->nextPC[tid]);
+ fromIEW->pc[tid].nextInstAddr());
commitStatus[tid] = ROBSquashing;
@@ -771,9 +765,7 @@ DefaultCommit<Impl>::commit()
toIEW->commitInfo[tid].branchTaken =
fromIEW->branchTaken[tid];
- toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
- toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
- toIEW->commitInfo[tid].nextMicroPC = fromIEW->nextMicroPC[tid];
+ toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
@@ -880,10 +872,7 @@ DefaultCommit<Impl>::commitInsts()
// Record that the number of ROB entries has changed.
changedROBNumEntries[tid] = true;
} else {
- PC[tid] = head_inst->readPC();
- nextPC[tid] = head_inst->readNextPC();
- nextNPC[tid] = head_inst->readNextNPC();
- nextMicroPC[tid] = head_inst->readNextMicroPC();
+ pc[tid] = head_inst->pcState();
// Increment the total number of non-speculative instructions
// executed.
@@ -911,11 +900,7 @@ DefaultCommit<Impl>::commitInsts()
cpu->instDone(tid);
}
- PC[tid] = nextPC[tid];
- nextPC[tid] = nextNPC[tid];
- nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
- microPC[tid] = nextMicroPC[tid];
- nextMicroPC[tid] = microPC[tid] + 1;
+ TheISA::advancePC(pc[tid], head_inst->staticInst);
int count = 0;
Addr oldpc;
@@ -923,19 +908,19 @@ DefaultCommit<Impl>::commitInsts()
// currently updating state while handling PC events.
assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
do {
- oldpc = PC[tid];
+ oldpc = pc[tid].instAddr();
cpu->system->pcEventQueue.service(thread[tid]->getTC());
count++;
- } while (oldpc != PC[tid]);
+ } while (oldpc != pc[tid].instAddr());
if (count > 1) {
DPRINTF(Commit,
"PC skip function event, stopping commit\n");
break;
}
} else {
- DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
+ DPRINTF(Commit, "Unable to commit head instruction PC:%s "
"[tid:%i] [sn:%i].\n",
- head_inst->readPC(), tid ,head_inst->seqNum);
+ head_inst->pcState(), tid ,head_inst->seqNum);
break;
}
}
@@ -970,8 +955,8 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
head_inst->isWriteBarrier()) {
DPRINTF(Commit, "Encountered a barrier or non-speculative "
- "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
- head_inst->seqNum, head_inst->readPC());
+ "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
+ head_inst->seqNum, head_inst->pcState());
if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
DPRINTF(Commit, "Waiting for all stores to writeback.\n");
@@ -994,8 +979,8 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
}
assert(head_inst->uncacheable());
- DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
- head_inst->seqNum, head_inst->readPC());
+ DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
+ head_inst->seqNum, head_inst->pcState());
// Send back the non-speculative instruction's sequence
// number. Tell the lsq to re-execute the load.
@@ -1034,8 +1019,8 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
#endif
if (inst_fault != NoFault) {
- DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
- head_inst->seqNum, head_inst->readPC());
+ DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
+ head_inst->seqNum, head_inst->pcState());
if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
@@ -1081,7 +1066,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
// Generate trap squash event.
generateTrapEvent(tid);
-// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
return false;
}
@@ -1089,9 +1073,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
#if FULL_SYSTEM
if (thread[tid]->profile) {
-// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
-// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
- thread[tid]->profilePC = head_inst->readPC();
+ thread[tid]->profilePC = head_inst->instAddr();
ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
head_inst->staticInst);
@@ -1101,7 +1083,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
if (CPA::available()) {
if (head_inst->isControl()) {
ThreadContext *tc = thread[tid]->getTC();
- CPA::cpa()->swAutoBegin(tc, head_inst->readNextPC());
+ CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
}
}
#endif
@@ -1154,8 +1136,8 @@ DefaultCommit<Impl>::getInsts()
commitStatus[tid] != TrapPending) {
changedROBNumEntries[tid] = true;
- DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
- inst->readPC(), inst->seqNum, tid);
+ DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
+ inst->pcState(), inst->seqNum, tid);
rob->insertInst(inst);
@@ -1163,9 +1145,9 @@ DefaultCommit<Impl>::getInsts()
youngestSeqNum[tid] = inst->seqNum;
} else {
- DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
+ DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
"squashed, skipping.\n",
- inst->readPC(), inst->seqNum, tid);
+ inst->pcState(), inst->seqNum, tid);
}
}
}
@@ -1181,14 +1163,14 @@ DefaultCommit<Impl>::skidInsert()
DynInstPtr inst = fromRename->insts[inst_num];
if (!inst->isSquashed()) {
- DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
- "skidBuffer.\n", inst->readPC(), inst->seqNum,
+ DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
+ "skidBuffer.\n", inst->pcState(), inst->seqNum,
inst->threadNumber);
skidBuffer.push(inst);
} else {
- DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
+ DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
"squashed, skipping.\n",
- inst->readPC(), inst->seqNum, inst->threadNumber);
+ inst->pcState(), inst->seqNum, inst->threadNumber);
}
}
}
@@ -1204,10 +1186,10 @@ DefaultCommit<Impl>::markCompletedInsts()
++inst_num)
{
if (!fromIEW->insts[inst_num]->isSquashed()) {
- DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
+ DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
"within ROB.\n",
fromIEW->insts[inst_num]->threadNumber,
- fromIEW->insts[inst_num]->readPC(),
+ fromIEW->insts[inst_num]->pcState(),
fromIEW->insts[inst_num]->seqNum);
// Mark the instruction as ready to commit.
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 8e9f3ef5d..21c5cc706 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -732,9 +732,7 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
//this->copyFromTC(tid);
//Set PC/NPC/NNPC
- setPC(src_tc->readPC(), tid);
- setNextPC(src_tc->readNextPC(), tid);
- setNextNPC(src_tc->readNextNPC(), tid);
+ pcState(src_tc->pcState(), tid);
src_tc->setStatus(ThreadContext::Active);
@@ -778,7 +776,7 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
// Squash Throughout Pipeline
InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
- fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid);
+ fetch.squash(0, squash_seq_num, tid);
decode.squash(tid);
rename.squash(squash_seq_num, tid);
iew.squash(tid);
@@ -1306,73 +1304,38 @@ FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
}
template <class Impl>
-uint64_t
-FullO3CPU<Impl>::readPC(ThreadID tid)
+TheISA::PCState
+FullO3CPU<Impl>::pcState(ThreadID tid)
{
- return commit.readPC(tid);
+ return commit.pcState(tid);
}
template <class Impl>
void
-FullO3CPU<Impl>::setPC(Addr new_PC, ThreadID tid)
-{
- commit.setPC(new_PC, tid);
-}
-
-template <class Impl>
-uint64_t
-FullO3CPU<Impl>::readMicroPC(ThreadID tid)
+FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
{
- return commit.readMicroPC(tid);
+ commit.pcState(val, tid);
}
template <class Impl>
-void
-FullO3CPU<Impl>::setMicroPC(Addr new_PC, ThreadID tid)
+Addr
+FullO3CPU<Impl>::instAddr(ThreadID tid)
{
- commit.setMicroPC(new_PC, tid);
+ return commit.instAddr(tid);
}
template <class Impl>
-uint64_t
-FullO3CPU<Impl>::readNextPC(ThreadID tid)
+Addr
+FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
{
- return commit.readNextPC(tid);
+ return commit.nextInstAddr(tid);
}
template <class Impl>
-void
-FullO3CPU<Impl>::setNextPC(uint64_t val, ThreadID tid)
-{
- commit.setNextPC(val, tid);
-}
-
-template <class Impl>
-uint64_t
-FullO3CPU<Impl>::readNextNPC(ThreadID tid)
-{
- return commit.readNextNPC(tid);
-}
-
-template <class Impl>
-void
-FullO3CPU<Impl>::setNextNPC(uint64_t val, ThreadID tid)
-{
- commit.setNextNPC(val, tid);
-}
-
-template <class Impl>
-uint64_t
-FullO3CPU<Impl>::readNextMicroPC(ThreadID tid)
-{
- return commit.readNextMicroPC(tid);
-}
-
-template <class Impl>
-void
-FullO3CPU<Impl>::setNextMicroPC(Addr new_PC, ThreadID tid)
+MicroPC
+FullO3CPU<Impl>::microPC(ThreadID tid)
{
- commit.setNextMicroPC(new_PC, tid);
+ return commit.microPC(tid);
}
template <class Impl>
@@ -1419,9 +1382,9 @@ template <class Impl>
void
FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
{
- DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
+ DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
"[sn:%lli]\n",
- inst->threadNumber, inst->readPC(), inst->seqNum);
+ inst->threadNumber, inst->pcState(), inst->seqNum);
removeInstsThisCycle = true;
@@ -1509,10 +1472,10 @@ FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
{
if ((*instIt)->threadNumber == tid) {
DPRINTF(O3CPU, "Squashing instruction, "
- "[tid:%i] [sn:%lli] PC %#x\n",
+ "[tid:%i] [sn:%lli] PC %s\n",
(*instIt)->threadNumber,
(*instIt)->seqNum,
- (*instIt)->readPC());
+ (*instIt)->pcState());
// Mark it as squashed.
(*instIt)->setSquashed();
@@ -1530,10 +1493,10 @@ FullO3CPU<Impl>::cleanUpRemovedInsts()
{
while (!removeList.empty()) {
DPRINTF(O3CPU, "Removing instruction, "
- "[tid:%i] [sn:%lli] PC %#x\n",
+ "[tid:%i] [sn:%lli] PC %s\n",
(*removeList.front())->threadNumber,
(*removeList.front())->seqNum,
- (*removeList.front())->readPC());
+ (*removeList.front())->pcState());
instList.erase(removeList.front());
@@ -1563,7 +1526,7 @@ FullO3CPU<Impl>::dumpInsts()
while (inst_list_it != instList.end()) {
cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
"Squashed:%i\n\n",
- num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
+ num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
(*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
(*inst_list_it)->isSquashed());
inst_list_it++;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 57c07a9ec..2669016ff 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -444,35 +444,20 @@ class FullO3CPU : public BaseO3CPU
void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
- /** Reads the commit PC of a specific thread. */
- Addr readPC(ThreadID tid);
+ /** Sets the commit PC state of a specific thread. */
+ void pcState(const TheISA::PCState &newPCState, ThreadID tid);
- /** Sets the commit PC of a specific thread. */
- void setPC(Addr new_PC, ThreadID tid);
+ /** Reads the commit PC state of a specific thread. */
+ TheISA::PCState pcState(ThreadID tid);
- /** Reads the commit micro PC of a specific thread. */
- Addr readMicroPC(ThreadID tid);
+ /** Reads the commit PC of a specific thread. */
+ Addr instAddr(ThreadID tid);
- /** Sets the commmit micro PC of a specific thread. */
- void setMicroPC(Addr new_microPC, ThreadID tid);
+ /** Reads the commit micro PC of a specific thread. */
+ MicroPC microPC(ThreadID tid);
/** Reads the next PC of a specific thread. */
- Addr readNextPC(ThreadID tid);
-
- /** Sets the next PC of a specific thread. */
- void setNextPC(Addr val, ThreadID tid);
-
- /** Reads the next NPC of a specific thread. */
- Addr readNextNPC(ThreadID tid);
-
- /** Sets the next NPC of a specific thread. */
- void setNextNPC(Addr val, ThreadID tid);
-
- /** Reads the commit next micro PC of a specific thread. */
- Addr readNextMicroPC(ThreadID tid);
-
- /** Sets the commit next micro PC of a specific thread. */
- void setNextMicroPC(Addr val, ThreadID tid);
+ Addr nextInstAddr(ThreadID tid);
/** Initiates a squash of all in-flight instructions for a given
* thread. The source of the squash is an external update of
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 1b76de132..5063e0f07 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -264,29 +264,16 @@ template<class Impl>
void
DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
{
- DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch prediction "
- "detected at decode.\n", tid, inst->seqNum);
+ DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
+ "prediction detected at decode.\n", tid, inst->seqNum);
// Send back mispredict information.
toFetch->decodeInfo[tid].branchMispredict = true;
toFetch->decodeInfo[tid].predIncorrect = true;
toFetch->decodeInfo[tid].squash = true;
toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
- toFetch->decodeInfo[tid].nextMicroPC = inst->readMicroPC();
-
-#if ISA_HAS_DELAY_SLOT
- toFetch->decodeInfo[tid].nextPC = inst->readPC() + sizeof(TheISA::MachInst);
- toFetch->decodeInfo[tid].nextNPC = inst->branchTarget();
- toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() !=
- (inst->readNextPC() + sizeof(TheISA::MachInst));
-#else
toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
- toFetch->decodeInfo[tid].nextNPC =
- inst->branchTarget() + sizeof(TheISA::MachInst);
- toFetch->decodeInfo[tid].branchTaken =
- inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
-#endif
-
+ toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
InstSeqNum squash_seq_num = inst->seqNum;
@@ -382,8 +369,8 @@ DefaultDecode<Impl>::skidInsert(ThreadID tid)
assert(tid == inst->threadNumber);
- DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n",
- inst->seqNum, inst->readPC(), inst->threadNumber);
+ DPRINTF(Decode,"Inserting [sn:%lli] PC: %s into decode skidBuffer %i\n",
+ inst->seqNum, inst->pcState(), inst->threadNumber);
skidBuffer[tid].push(inst);
}
@@ -681,13 +668,12 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
insts_to_decode.pop();
DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
- "PC %#x\n",
- tid, inst->seqNum, inst->readPC());
+ "PC %s\n", tid, inst->seqNum, inst->pcState());
if (inst->isSquashed()) {
- DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is "
+ DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is "
"squashed, skipping.\n",
- tid, inst->seqNum, inst->readPC());
+ tid, inst->seqNum, inst->pcState());
++decodeSquashedInsts;
@@ -717,9 +703,6 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
// Ensure that if it was predicted as a branch, it really is a
// branch.
if (inst->readPredTaken() && !inst->isControl()) {
- DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n",
- inst->readPredPC(), inst->readNextPC() + 4);
-
panic("Instruction predicted as a branch!");
++decodeControlMispred;
@@ -735,26 +718,18 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
++decodeBranchResolved;
- if (inst->branchTarget() != inst->readPredPC()) {
+ if (!(inst->branchTarget() == inst->readPredTarg())) {
++decodeBranchMispred;
// Might want to set some sort of boolean and just do
// a check at the end
squash(inst, inst->threadNumber);
- Addr target = inst->branchTarget();
+ TheISA::PCState target = inst->branchTarget();
-#if ISA_HAS_DELAY_SLOT
- DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %#x PredNextPC: %#x\n",
- inst->seqNum, inst->readPC() + sizeof(TheISA::MachInst), target);
-
- //The micro pc after an instruction level branch should be 0
- inst->setPredTarg(inst->readPC() + sizeof(TheISA::MachInst), target, 0);
-#else
- DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %#x PredNextPC: %#x\n",
- inst->seqNum, target, target + sizeof(TheISA::MachInst));
+ DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n",
+ inst->seqNum, target);
//The micro pc after an instruction level branch should be 0
- inst->setPredTarg(target, target + sizeof(TheISA::MachInst), 0);
-#endif
+ inst->setPredTarg(target);
break;
}
}
diff --git a/src/cpu/o3/dep_graph.hh b/src/cpu/o3/dep_graph.hh
index c19fd0abf..804b3f9cd 100644
--- a/src/cpu/o3/dep_graph.hh
+++ b/src/cpu/o3/dep_graph.hh
@@ -251,8 +251,8 @@ DependencyGraph<DynInstPtr>::dump()
curr = &dependGraph[i];
if (curr->inst) {
- cprintf("dependGraph[%i]: producer: %#x [sn:%lli] consumer: ",
- i, curr->inst->readPC(), curr->inst->seqNum);
+ cprintf("dependGraph[%i]: producer: %s [sn:%lli] consumer: ",
+ i, curr->inst->pcState(), curr->inst->seqNum);
} else {
cprintf("dependGraph[%i]: No producer. consumer: ", i);
}
@@ -260,8 +260,8 @@ DependencyGraph<DynInstPtr>::dump()
while (curr->next != NULL) {
curr = curr->next;
- cprintf("%#x [sn:%lli] ",
- curr->inst->readPC(), curr->inst->seqNum);
+ cprintf("%s [sn:%lli] ",
+ curr->inst->pcState(), curr->inst->seqNum);
}
cprintf("\n");
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index e1279f82b..6bd1f9fad 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -74,14 +74,14 @@ class BaseO3DynInst : public BaseDynInst<Impl>
public:
/** BaseDynInst constructor given a binary instruction. */
- BaseO3DynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
- Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC,
- InstSeqNum seq_num, O3CPU *cpu);
+ BaseO3DynInst(StaticInstPtr staticInst,
+ TheISA::PCState pc, TheISA::PCState predPC,
+ InstSeqNum seq_num, O3CPU *cpu);
/** BaseDynInst constructor given a binary instruction. */
- BaseO3DynInst(ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
- Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC,
- InstSeqNum seq_num, O3CPU *cpu);
+ BaseO3DynInst(ExtMachInst inst,
+ TheISA::PCState pc, TheISA::PCState predPC,
+ InstSeqNum seq_num, O3CPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
BaseO3DynInst(StaticInstPtr &_staticInst);
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 3e015d962..6f7c23b2f 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -33,24 +33,18 @@
template <class Impl>
BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
- Addr PC, Addr NPC, Addr microPC,
- Addr Pred_PC, Addr Pred_NPC,
- Addr Pred_MicroPC,
+ TheISA::PCState pc, TheISA::PCState predPC,
InstSeqNum seq_num, O3CPU *cpu)
- : BaseDynInst<Impl>(staticInst, PC, NPC, microPC,
- Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu)
+ : BaseDynInst<Impl>(staticInst, pc, predPC, seq_num, cpu)
{
initVars();
}
template <class Impl>
BaseO3DynInst<Impl>::BaseO3DynInst(ExtMachInst inst,
- Addr PC, Addr NPC, Addr microPC,
- Addr Pred_PC, Addr Pred_NPC,
- Addr Pred_MicroPC,
+ TheISA::PCState pc, TheISA::PCState predPC,
InstSeqNum seq_num, O3CPU *cpu)
- : BaseDynInst<Impl>(inst, PC, NPC, microPC,
- Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu)
+ : BaseDynInst<Impl>(inst, pc, predPC, seq_num, cpu)
{
initVars();
}
@@ -131,15 +125,17 @@ BaseO3DynInst<Impl>::hwrei()
{
#if THE_ISA == ALPHA_ISA
// Can only do a hwrei when in pal mode.
- if (!(this->readPC() & 0x3))
+ if (!(this->instAddr() & 0x3))
return new AlphaISA::UnimplementedOpcodeFault;
// Set the next PC based on the value of the EXC_ADDR IPR.
- this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
- this->threadNumber));
+ AlphaISA::PCState pc = this->pcState();
+ pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
+ this->threadNumber));
+ this->pcState(pc);
if (CPA::available()) {
ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
- CPA::cpa()->swAutoBegin(tc, this->readNextPC());
+ CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
}
// Tell CPU to clear any state it needs to if a hwrei is taken.
@@ -175,11 +171,11 @@ BaseO3DynInst<Impl>::syscall(int64_t callnum)
// HACK: check CPU's nextPC before and after syscall. If it
// changes, update this instruction's nextPC because the syscall
// must have changed the nextPC.
- Addr cpu_next_pc = this->cpu->readNextPC(this->threadNumber);
+ TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
this->cpu->syscall(callnum, this->threadNumber);
- Addr new_next_pc = this->cpu->readNextPC(this->threadNumber);
- if (cpu_next_pc != new_next_pc) {
- this->setNextPC(new_next_pc);
+ TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
+ if (!(curPC == newPC)) {
+ this->pcState(newPC);
}
}
#endif
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index d881c291f..22e9e51b4 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -229,7 +229,7 @@ class DefaultFetch
* @param next_NPC Used for ISAs which use delay slots.
* @return Whether or not a branch was predicted as taken.
*/
- bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC, Addr &next_MicroPC);
+ bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
/**
* Fetches the cache line that contains fetch_PC. Returns any
@@ -244,14 +244,12 @@ class DefaultFetch
bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid);
/** Squashes a specific thread and resets the PC. */
- inline void doSquash(const Addr &new_PC, const Addr &new_NPC,
- const Addr &new_MicroPC, ThreadID tid);
+ inline void doSquash(const TheISA::PCState &newPC, ThreadID tid);
/** Squashes a specific thread and resets the PC. Also tells the CPU to
* remove any instructions between fetch and decode that should be sqaushed.
*/
- void squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
- const Addr &new_MicroPC,
+ void squashFromDecode(const TheISA::PCState &newPC,
const InstSeqNum &seq_num, ThreadID tid);
/** Checks if a thread is stalled. */
@@ -266,8 +264,7 @@ class DefaultFetch
* remove any instructions that are not in the ROB. The source of this
* squash should be the commit stage.
*/
- void squash(const Addr &new_PC, const Addr &new_NPC,
- const Addr &new_MicroPC,
+ void squash(const TheISA::PCState &newPC,
const InstSeqNum &seq_num, ThreadID tid);
/** Ticks the fetch stage, processing all inputs signals and fetching
@@ -348,14 +345,7 @@ class DefaultFetch
/** Predecoder. */
TheISA::Predecoder predecoder;
- /** Per-thread fetch PC. */
- Addr PC[Impl::MaxThreads];
-
- /** Per-thread fetch micro PC. */
- Addr microPC[Impl::MaxThreads];
-
- /** Per-thread next PC. */
- Addr nextPC[Impl::MaxThreads];
+ TheISA::PCState pc[Impl::MaxThreads];
/** Memory request used to access cache. */
RequestPtr memReq[Impl::MaxThreads];
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 3f8f84cab..bbd9ce4a2 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -316,9 +316,7 @@ DefaultFetch<Impl>::initStage()
{
// Setup PC and nextPC with initial state.
for (ThreadID tid = 0; tid < numThreads; tid++) {
- PC[tid] = cpu->readPC(tid);
- nextPC[tid] = cpu->readNextPC(tid);
- microPC[tid] = cpu->readMicroPC(tid);
+ pc[tid] = cpu->pcState(tid);
}
for (ThreadID tid = 0; tid < numThreads; tid++) {
@@ -445,9 +443,7 @@ DefaultFetch<Impl>::takeOverFrom()
stalls[i].rename = 0;
stalls[i].iew = 0;
stalls[i].commit = 0;
- PC[i] = cpu->readPC(i);
- nextPC[i] = cpu->readNextPC(i);
- microPC[i] = cpu->readMicroPC(i);
+ pc[i] = cpu->pcState(i);
fetchStatus[i] = Running;
}
numInst = 0;
@@ -496,8 +492,8 @@ DefaultFetch<Impl>::switchToInactive()
template <class Impl>
bool
-DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
- Addr &next_NPC, Addr &next_MicroPC)
+DefaultFetch<Impl>::lookupAndUpdateNextPC(
+ DynInstPtr &inst, TheISA::PCState &nextPC)
{
// Do branch prediction check here.
// A bit of a misnomer...next_PC is actually the current PC until
@@ -505,51 +501,26 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
bool predict_taken;
if (!inst->isControl()) {
- if (inst->isMicroop() && !inst->isLastMicroop()) {
- next_MicroPC++;
- } else {
- next_PC = next_NPC;
- next_NPC = next_NPC + instSize;
- next_MicroPC = 0;
- }
- inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
+ TheISA::advancePC(nextPC, inst->staticInst);
+ inst->setPredTarg(nextPC);
inst->setPredTaken(false);
return false;
}
- //Assume for now that all control flow is to a different macroop which
- //would reset the micro pc to 0.
- next_MicroPC = 0;
-
ThreadID tid = inst->threadNumber;
- Addr pred_PC = next_PC;
- predict_taken = branchPred.predict(inst, pred_PC, tid);
+ predict_taken = branchPred.predict(inst, nextPC, tid);
if (predict_taken) {
- DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %#x.\n",
- tid, inst->seqNum, pred_PC);
+ DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n",
+ tid, inst->seqNum, nextPC);
} else {
DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
tid, inst->seqNum);
}
-#if ISA_HAS_DELAY_SLOT
- next_PC = next_NPC;
- if (predict_taken)
- next_NPC = pred_PC;
- else
- next_NPC += instSize;
-#else
- if (predict_taken)
- next_PC = pred_PC;
- else
- next_PC += instSize;
- next_NPC = next_PC + instSize;
-#endif
-
- DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %#x and then %#x.\n",
- tid, inst->seqNum, next_PC, next_NPC);
- inst->setPredTarg(next_PC, next_NPC, next_MicroPC);
+ DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
+ tid, inst->seqNum, nextPC);
+ inst->setPredTarg(nextPC);
inst->setPredTaken(predict_taken);
++fetchedBranches;
@@ -668,15 +639,12 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid
template <class Impl>
inline void
-DefaultFetch<Impl>::doSquash(const Addr &new_PC,
- const Addr &new_NPC, const Addr &new_microPC, ThreadID tid)
+DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
{
- DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
- tid, new_PC, new_NPC);
+ DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
+ tid, newPC);
- PC[tid] = new_PC;
- nextPC[tid] = new_NPC;
- microPC[tid] = new_microPC;
+ pc[tid] = newPC;
// Clear the icache miss if it's outstanding.
if (fetchStatus[tid] == IcacheWaitResponse) {
@@ -703,13 +671,12 @@ DefaultFetch<Impl>::doSquash(const Addr &new_PC,
template<class Impl>
void
-DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
- const Addr &new_MicroPC,
+DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
const InstSeqNum &seq_num, ThreadID tid)
{
- DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
+ DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
- doSquash(new_PC, new_NPC, new_MicroPC, tid);
+ doSquash(newPC, tid);
// Tell the CPU to remove any instructions that are in flight between
// fetch and decode.
@@ -784,13 +751,12 @@ DefaultFetch<Impl>::updateFetchStatus()
template <class Impl>
void
-DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
- const Addr &new_MicroPC,
+DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
const InstSeqNum &seq_num, ThreadID tid)
{
- DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
+ DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
- doSquash(new_PC, new_NPC, new_MicroPC, tid);
+ doSquash(newPC, tid);
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid);
@@ -903,16 +869,14 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
"from commit.\n",tid);
// In any case, squash.
- squash(fromCommit->commitInfo[tid].nextPC,
- fromCommit->commitInfo[tid].nextNPC,
- fromCommit->commitInfo[tid].nextMicroPC,
+ squash(fromCommit->commitInfo[tid].pc,
fromCommit->commitInfo[tid].doneSeqNum,
tid);
// Also check if there's a mispredict that happened.
if (fromCommit->commitInfo[tid].branchMispredict) {
branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
- fromCommit->commitInfo[tid].nextPC,
+ fromCommit->commitInfo[tid].pc,
fromCommit->commitInfo[tid].branchTaken,
tid);
} else {
@@ -955,13 +919,10 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
if (fetchStatus[tid] != Squashing) {
- DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
- fromDecode->decodeInfo[tid].nextPC,
- fromDecode->decodeInfo[tid].nextNPC);
+ TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC;
+ DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
// Squash unless we're already squashing
squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
- fromDecode->decodeInfo[tid].nextNPC,
- fromDecode->decodeInfo[tid].nextMicroPC,
fromDecode->decodeInfo[tid].doneSeqNum,
tid);
@@ -1016,9 +977,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
// The current PC.
- Addr fetch_PC = PC[tid];
- Addr fetch_NPC = nextPC[tid];
- Addr fetch_MicroPC = microPC[tid];
+ TheISA::PCState fetchPC = pc[tid];
// Fault code for memory access.
Fault fault = NoFault;
@@ -1034,10 +993,9 @@ DefaultFetch<Impl>::fetch(bool &status_change)
status_change = true;
} else if (fetchStatus[tid] == Running) {
DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
- "instruction, starting at PC %08p.\n",
- tid, fetch_PC);
+ "instruction, starting at PC %s.\n", tid, fetchPC);
- bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
+ bool fetch_success = fetchCacheLine(fetchPC.instAddr(), fault, tid);
if (!fetch_success) {
if (cacheBlocked) {
++icacheStallCycles;
@@ -1075,20 +1033,21 @@ DefaultFetch<Impl>::fetch(bool &status_change)
return;
}
- Addr next_PC = fetch_PC;
- Addr next_NPC = fetch_NPC;
- Addr next_MicroPC = fetch_MicroPC;
+ TheISA::PCState nextPC = fetchPC;
InstSeqNum inst_seq;
MachInst inst;
ExtMachInst ext_inst;
- // @todo: Fix this hack.
- unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
StaticInstPtr staticInst = NULL;
StaticInstPtr macroop = NULL;
if (fault == NoFault) {
+ //XXX Masking out pal mode bit. This will break x86. Alpha needs
+ //to pull the pal mode bit ouf ot the instruction address.
+ unsigned offset = (fetchPC.instAddr() & ~1) - cacheDataPC[tid];
+ assert(offset < cacheBlkSize);
+
// If the read of the first instruction was successful, then grab the
// instructions from the rest of the cache line and put them into the
// queue heading to decode.
@@ -1104,15 +1063,6 @@ DefaultFetch<Impl>::fetch(bool &status_change)
numInst < fetchWidth &&
!predicted_branch) {
- // If we're branching after this instruction, quite fetching
- // from the same block then.
- predicted_branch =
- (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
- if (predicted_branch) {
- DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n",
- fetch_PC, fetch_NPC);
- }
-
// Make sure this is a valid index.
assert(offset <= cacheBlkSize - instSize);
@@ -1122,16 +1072,16 @@ DefaultFetch<Impl>::fetch(bool &status_change)
(&cacheData[tid][offset]));
predecoder.setTC(cpu->thread[tid]->getTC());
- predecoder.moreBytes(fetch_PC, fetch_PC, inst);
+ predecoder.moreBytes(fetchPC, fetchPC.instAddr(), inst);
- ext_inst = predecoder.getExtMachInst();
- staticInst = StaticInstPtr(ext_inst, fetch_PC);
+ ext_inst = predecoder.getExtMachInst(fetchPC);
+ staticInst = StaticInstPtr(ext_inst, fetchPC.instAddr());
if (staticInst->isMacroop())
macroop = staticInst;
}
do {
if (macroop) {
- staticInst = macroop->fetchMicroop(fetch_MicroPC);
+ staticInst = macroop->fetchMicroop(fetchPC.microPC());
if (staticInst->isLastMicroop())
macroop = NULL;
}
@@ -1141,8 +1091,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
// Create a new DynInst from the instruction fetched.
DynInstPtr instruction = new DynInst(staticInst,
- fetch_PC, fetch_NPC, fetch_MicroPC,
- next_PC, next_NPC, next_MicroPC,
+ fetchPC, nextPC,
inst_seq, cpu);
instruction->setTid(tid);
@@ -1150,27 +1099,32 @@ DefaultFetch<Impl>::fetch(bool &status_change)
instruction->setThreadState(cpu->thread[tid]);
- DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
- "[sn:%lli]\n", tid, instruction->readPC(),
- instruction->readMicroPC(), inst_seq);
+ DPRINTF(Fetch, "[tid:%i]: Instruction PC %s (%d) created "
+ "[sn:%lli]\n", tid, instruction->pcState(),
+ instruction->microPC(), inst_seq);
//DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
- DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
- tid, instruction->staticInst->disassemble(fetch_PC));
+ DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
+ instruction->staticInst->
+ disassemble(fetchPC.instAddr()));
#if TRACING_ON
instruction->traceData =
cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
- instruction->staticInst, instruction->readPC(),
- macroop, instruction->readMicroPC());
+ instruction->staticInst, fetchPC, macroop);
#else
instruction->traceData = NULL;
#endif
- ///FIXME This needs to be more robust in dealing with delay slots
+ // If we're branching after this instruction, quite fetching
+ // from the same block then.
+ predicted_branch = fetchPC.branching();
predicted_branch |=
- lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC);
+ lookupAndUpdateNextPC(instruction, nextPC);
+ if (predicted_branch) {
+ DPRINTF(Fetch, "Branch detected with PC = %s\n", fetchPC);
+ }
// Add instruction to the CPU's list of instructions.
instruction->setInstListIt(cpu->addInst(instruction));
@@ -1185,9 +1139,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
++fetchedInsts;
// Move to the next instruction, unless we have a branch.
- fetch_PC = next_PC;
- fetch_NPC = next_NPC;
- fetch_MicroPC = next_MicroPC;
+ fetchPC = nextPC;
if (instruction->isQuiesce()) {
DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
@@ -1202,7 +1154,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
} while (staticInst->isMicroop() &&
!staticInst->isLastMicroop() &&
numInst < fetchWidth);
- offset += instSize;
+ //XXX Masking out pal mode bit.
+ offset = (fetchPC.instAddr() & ~1) - cacheDataPC[tid];
}
if (predicted_branch) {
@@ -1224,10 +1177,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
// Now that fetching is completed, update the PC to signify what the next
// cycle will be.
if (fault == NoFault) {
- PC[tid] = next_PC;
- nextPC[tid] = next_NPC;
- microPC[tid] = next_MicroPC;
- DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
+ pc[tid] = nextPC;
+ DPRINTF(Fetch, "[tid:%i]: Setting PC to %s.\n", tid, nextPC);
} else {
// We shouldn't be in an icache miss and also have a fault (an ITB
// miss)
@@ -1245,11 +1196,10 @@ DefaultFetch<Impl>::fetch(bool &status_change)
ext_inst = TheISA::NoopMachInst;
// Create a new DynInst from the dummy nop.
- DynInstPtr instruction = new DynInst(ext_inst,
- fetch_PC, fetch_NPC, fetch_MicroPC,
- next_PC, next_NPC, next_MicroPC,
+ DynInstPtr instruction = new DynInst(ext_inst, fetchPC, nextPC,
inst_seq, cpu);
- instruction->setPredTarg(next_NPC, next_NPC + instSize, 0);
+ TheISA::advancePC(nextPC, instruction->staticInst);
+ instruction->setPredTarg(nextPC);
instruction->setTid(tid);
instruction->setASID(tid);
@@ -1272,8 +1222,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
fetchStatus[tid] = TrapPending;
status_change = true;
- DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
- tid, fault->name(), PC[tid]);
+ DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s",
+ tid, fault->name(), pc[tid]);
}
}
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 2089913ef..608e70cde 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -449,27 +449,18 @@ template<class Impl>
void
DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
{
- DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
- "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
+ DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
+ "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum;
- toCommit->mispredPC[tid] = inst->readPC();
+ toCommit->mispredPC[tid] = inst->instAddr();
toCommit->branchMispredict[tid] = true;
-#if ISA_HAS_DELAY_SLOT
- int instSize = sizeof(TheISA::MachInst);
- toCommit->branchTaken[tid] =
- !(inst->readNextPC() + instSize == inst->readNextNPC() &&
- (inst->readNextPC() == inst->readPC() + instSize ||
- inst->readNextPC() == inst->readPC() + 2 * instSize));
-#else
- toCommit->branchTaken[tid] = inst->readNextPC() !=
- (inst->readPC() + sizeof(TheISA::MachInst));
-#endif
- toCommit->nextPC[tid] = inst->readNextPC();
- toCommit->nextNPC[tid] = inst->readNextNPC();
- toCommit->nextMicroPC[tid] = inst->readNextMicroPC();
+ toCommit->branchTaken[tid] = inst->pcState().branching();
+ TheISA::PCState pc = inst->pcState();
+ TheISA::advancePC(pc, inst->staticInst);
+ toCommit->pc[tid] = pc;
toCommit->includeSquashInst[tid] = false;
@@ -481,12 +472,13 @@ void
DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
{
DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
- "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
+ "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum;
- toCommit->nextPC[tid] = inst->readNextPC();
- toCommit->nextNPC[tid] = inst->readNextNPC();
+ TheISA::PCState pc = inst->pcState();
+ TheISA::advancePC(pc, inst->staticInst);
+ toCommit->pc[tid] = pc;
toCommit->branchMispredict[tid] = false;
toCommit->includeSquashInst[tid] = false;
@@ -499,12 +491,11 @@ void
DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
{
DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
- "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
+ "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum;
- toCommit->nextPC[tid] = inst->readPC();
- toCommit->nextNPC[tid] = inst->readNextPC();
+ toCommit->pc[tid] = inst->pcState();
toCommit->branchMispredict[tid] = false;
// Must include the broadcasted SN in the squash.
@@ -628,9 +619,9 @@ DefaultIEW<Impl>::skidInsert(ThreadID tid)
insts[tid].pop();
- DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
+ DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
"dispatch skidBuffer %i\n",tid, inst->seqNum,
- inst->readPC(),tid);
+ inst->pcState(),tid);
skidBuffer[tid].push(inst);
}
@@ -986,9 +977,9 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
// Make sure there's a valid instruction there.
assert(inst);
- DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
+ DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
"IQ.\n",
- tid, inst->readPC(), inst->seqNum, inst->threadNumber);
+ tid, inst->pcState(), inst->seqNum, inst->threadNumber);
// Be sure to mark these instructions as ready so that the
// commit stage can go ahead and execute them, and mark
@@ -1165,7 +1156,7 @@ DefaultIEW<Impl>::printAvailableInsts()
if (inst%3==0) std::cout << "\n\t";
- std::cout << "PC: " << fromIssue->insts[inst]->readPC()
+ std::cout << "PC: " << fromIssue->insts[inst]->pcState()
<< " TN: " << fromIssue->insts[inst]->threadNumber
<< " SN: " << fromIssue->insts[inst]->seqNum << " | ";
@@ -1205,8 +1196,8 @@ DefaultIEW<Impl>::executeInsts()
DynInstPtr inst = instQueue.getInstToExecute();
- DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
- inst->readPC(), inst->threadNumber,inst->seqNum);
+ DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
+ inst->pcState(), inst->threadNumber,inst->seqNum);
// Check if the instruction is squashed; if so then skip it
if (inst->isSquashed()) {
@@ -1298,10 +1289,9 @@ DefaultIEW<Impl>::executeInsts()
DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
- inst->readPredPC(), inst->readPredNPC());
- DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
- " NPC: %#x.\n", inst->readNextPC(),
- inst->readNextNPC());
+ inst->predInstAddr(), inst->predNextInstAddr());
+ DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
+ inst->pcState(), inst->nextInstAddr());
// If incorrect, then signal the ROB that it must be squashed.
squashDueToBranch(inst, tid);
@@ -1318,16 +1308,11 @@ DefaultIEW<Impl>::executeInsts()
DynInstPtr violator;
violator = ldstQueue.getMemDepViolator(tid);
- DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %#x "
- "[sn:%lli], inst PC: %#x [sn:%lli]. Addr is: %#x.\n",
- violator->readPC(), violator->seqNum,
- inst->readPC(), inst->seqNum, inst->physEffAddr);
- // Ensure the violating instruction is older than
- // current squash
-/* if (fetchRedirect[tid] &&
- violator->seqNum >= toCommit->squashedSeqNum[tid] + 1)
- continue;
-*/
+ DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
+ "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
+ violator->pcState(), violator->seqNum,
+ inst->pcState(), inst->seqNum, inst->physEffAddr);
+
fetchRedirect[tid] = true;
// Tell the instruction queue that a violation has occured.
@@ -1342,8 +1327,8 @@ DefaultIEW<Impl>::executeInsts()
fetchRedirect[tid] = true;
DPRINTF(IEW, "Load operation couldn't execute because the "
- "memory system is blocked. PC: %#x [sn:%lli]\n",
- inst->readPC(), inst->seqNum);
+ "memory system is blocked. PC: %s [sn:%lli]\n",
+ inst->pcState(), inst->seqNum);
squashDueToMemBlocked(inst, tid);
}
@@ -1356,8 +1341,9 @@ DefaultIEW<Impl>::executeInsts()
DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
- "%#x, inst PC: %#x. Addr is: %#x.\n",
- violator->readPC(), inst->readPC(), inst->physEffAddr);
+ "%s, inst PC: %s. Addr is: %#x.\n",
+ violator->pcState(), inst->pcState(),
+ inst->physEffAddr);
DPRINTF(IEW, "Violation will not be handled because "
"already squashing\n");
@@ -1366,8 +1352,8 @@ DefaultIEW<Impl>::executeInsts()
if (ldstQueue.loadBlocked(tid) &&
!ldstQueue.isLoadBlockedHandled(tid)) {
DPRINTF(IEW, "Load operation couldn't execute because the "
- "memory system is blocked. PC: %#x [sn:%lli]\n",
- inst->readPC(), inst->seqNum);
+ "memory system is blocked. PC: %s [sn:%lli]\n",
+ inst->pcState(), inst->seqNum);
DPRINTF(IEW, "Blocked load will not be handled because "
"already squashing\n");
@@ -1408,8 +1394,8 @@ DefaultIEW<Impl>::writebackInsts()
DynInstPtr inst = toCommit->insts[inst_num];
ThreadID tid = inst->threadNumber;
- DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
- inst->seqNum, inst->readPC());
+ DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
+ inst->seqNum, inst->pcState());
iewInstsToCommit[tid]++;
@@ -1613,10 +1599,10 @@ DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
- inst->readPredPC(), inst->readPredNPC());
+ inst->predInstAddr(), inst->predNextInstAddr());
DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
- " NPC: %#x.\n", inst->readNextPC(),
- inst->readNextNPC());
+ " NPC: %#x.\n", inst->nextInstAddr(),
+ inst->nextInstAddr());
// If incorrect, then signal the ROB that it must be squashed.
squashDueToBranch(inst, tid);
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 3d5eadf84..b944979f2 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -504,8 +504,8 @@ InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
// Make sure the instruction is valid
assert(new_inst);
- DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n",
- new_inst->seqNum, new_inst->readPC());
+ DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n",
+ new_inst->seqNum, new_inst->pcState());
assert(freeEntries != 0);
@@ -547,9 +547,9 @@ InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
nonSpecInsts[new_inst->seqNum] = new_inst;
- DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x "
+ DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s "
"to the IQ.\n",
- new_inst->seqNum, new_inst->readPC());
+ new_inst->seqNum, new_inst->pcState());
assert(freeEntries != 0);
@@ -767,9 +767,9 @@ InstructionQueue<Impl>::scheduleReadyInsts()
}
}
- DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
+ DPRINTF(IQ, "Thread %i: Issuing instruction PC %s "
"[sn:%lli]\n",
- tid, issuing_inst->readPC(),
+ tid, issuing_inst->pcState(),
issuing_inst->seqNum);
readyInsts[op_class].pop();
@@ -910,7 +910,7 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
while (dep_inst) {
DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
- "PC%#x.\n", dep_inst->seqNum, dep_inst->readPC());
+ "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
// Might want to give more information to the instruction
// so that it knows which of its source registers is
@@ -955,8 +955,8 @@ InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
}
DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
- "the ready list, PC %#x opclass:%i [sn:%lli].\n",
- ready_inst->readPC(), op_class, ready_inst->seqNum);
+ "the ready list, PC %s opclass:%i [sn:%lli].\n",
+ ready_inst->pcState(), op_class, ready_inst->seqNum);
}
template <class Impl>
@@ -981,8 +981,8 @@ InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
{
ThreadID tid = completed_inst->threadNumber;
- DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
- completed_inst->readPC(), completed_inst->seqNum);
+ DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n",
+ completed_inst->pcState(), completed_inst->seqNum);
++freeEntries;
@@ -1050,9 +1050,8 @@ InstructionQueue<Impl>::doSquash(ThreadID tid)
(squashed_inst->isMemRef() &&
!squashed_inst->memOpDone)) {
- DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
- "squashed.\n",
- tid, squashed_inst->seqNum, squashed_inst->readPC());
+ DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
+ tid, squashed_inst->seqNum, squashed_inst->pcState());
// Remove the instruction from the dependency list.
if (!squashed_inst->isNonSpeculative() &&
@@ -1147,9 +1146,9 @@ InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
if (src_reg >= numPhysRegs) {
continue;
} else if (regScoreboard[src_reg] == false) {
- DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
+ DPRINTF(IQ, "Instruction PC %s has src reg %i that "
"is being added to the dependency chain.\n",
- new_inst->readPC(), src_reg);
+ new_inst->pcState(), src_reg);
dependGraph.insert(src_reg, new_inst);
@@ -1157,9 +1156,9 @@ InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
// was added to the dependency graph.
return_val = true;
} else {
- DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
+ DPRINTF(IQ, "Instruction PC %s has src reg %i that "
"became ready before it reached the IQ.\n",
- new_inst->readPC(), src_reg);
+ new_inst->pcState(), src_reg);
// Mark a register ready within the instruction.
new_inst->markSrcRegReady(src_reg_idx);
}
@@ -1228,8 +1227,8 @@ InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
OpClass op_class = inst->opClass();
DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
- "the ready list, PC %#x opclass:%i [sn:%lli].\n",
- inst->readPC(), op_class, inst->seqNum);
+ "the ready list, PC %s opclass:%i [sn:%lli].\n",
+ inst->pcState(), op_class, inst->seqNum);
readyInsts[op_class].push(inst);
@@ -1299,7 +1298,7 @@ InstructionQueue<Impl>::dumpLists()
cprintf("Non speculative list: ");
while (non_spec_it != non_spec_end_it) {
- cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
+ cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(),
(*non_spec_it).second->seqNum);
++non_spec_it;
}
@@ -1348,9 +1347,9 @@ InstructionQueue<Impl>::dumpInsts()
}
}
- cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
"Issued:%i\nSquashed:%i\n",
- (*inst_list_it)->readPC(),
+ (*inst_list_it)->pcState(),
(*inst_list_it)->seqNum,
(*inst_list_it)->threadNumber,
(*inst_list_it)->isIssued(),
@@ -1390,9 +1389,9 @@ InstructionQueue<Impl>::dumpInsts()
}
}
- cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
"Issued:%i\nSquashed:%i\n",
- (*inst_list_it)->readPC(),
+ (*inst_list_it)->pcState(),
(*inst_list_it)->seqNum,
(*inst_list_it)->threadNumber,
(*inst_list_it)->isIssued(),
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index a9047558d..372e76b71 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -530,8 +530,8 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
(load_idx != loadHead || !load_inst->isAtCommit())) {
iewStage->rescheduleMemInst(load_inst);
++lsqRescheduledLoads;
- DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %#x\n",
- load_inst->seqNum, load_inst->readPC());
+ DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n",
+ load_inst->seqNum, load_inst->pcState());
// Must delete request now that it wasn't handed off to
// memory. This is quite ugly. @todo: Figure out the proper
@@ -687,8 +687,8 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
}
// If there's no forwarding case, then go access memory
- DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n",
- load_inst->seqNum, load_inst->readPC());
+ DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n",
+ load_inst->seqNum, load_inst->pcState());
assert(!load_inst->memData);
load_inst->memData = new uint8_t[64];
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 8aa7fe397..345d3ea69 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -352,8 +352,8 @@ LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
assert((loadTail + 1) % LQEntries != loadHead);
assert(loads < LQEntries);
- DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
- load_inst->readPC(), loadTail, load_inst->seqNum);
+ DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
+ load_inst->pcState(), loadTail, load_inst->seqNum);
load_inst->lqIdx = loadTail;
@@ -378,8 +378,8 @@ LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
assert((storeTail + 1) % SQEntries != storeHead);
assert(stores < SQEntries);
- DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
- store_inst->readPC(), storeTail, store_inst->seqNum);
+ DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
+ store_inst->pcState(), storeTail, store_inst->seqNum);
store_inst->sqIdx = storeTail;
store_inst->lqIdx = loadTail;
@@ -444,8 +444,8 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
// Execute a specific load.
Fault load_fault = NoFault;
- DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
- inst->readPC(),inst->seqNum);
+ DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
+ inst->pcState(),inst->seqNum);
assert(!inst->isSquashed());
@@ -519,8 +519,8 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
int store_idx = store_inst->sqIdx;
- DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
- store_inst->readPC(), store_inst->seqNum);
+ DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n",
+ store_inst->pcState(), store_inst->seqNum);
assert(!store_inst->isSquashed());
@@ -531,8 +531,8 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
Fault store_fault = store_inst->initiateAcc();
if (storeQueue[store_idx].size == 0) {
- DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
- store_inst->readPC(),store_inst->seqNum);
+ DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli],Size = 0\n",
+ store_inst->pcState(), store_inst->seqNum);
return store_fault;
}
@@ -593,8 +593,8 @@ LSQUnit<Impl>::commitLoad()
{
assert(loadQueue[loadHead]);
- DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
- loadQueue[loadHead]->readPC());
+ DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n",
+ loadQueue[loadHead]->pcState());
loadQueue[loadHead] = NULL;
@@ -631,8 +631,8 @@ LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
break;
}
DPRINTF(LSQUnit, "Marking store as able to write back, PC "
- "%#x [sn:%lli]\n",
- storeQueue[store_idx].inst->readPC(),
+ "%s [sn:%lli]\n",
+ storeQueue[store_idx].inst->pcState(),
storeQueue[store_idx].inst->seqNum);
storeQueue[store_idx].canWB = true;
@@ -757,9 +757,9 @@ LSQUnit<Impl>::writebackStores()
req = sreqLow;
}
- DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
+ DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
"to Addr:%#x, data:%#x [sn:%lli]\n",
- storeWBIdx, inst->readPC(),
+ storeWBIdx, inst->pcState(),
req->getPaddr(), (int)*(inst->memData),
inst->seqNum);
@@ -861,9 +861,9 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
decrLdIdx(load_idx);
while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
- DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
+ DPRINTF(LSQUnit,"Load Instruction PC %s squashed, "
"[sn:%lli]\n",
- loadQueue[load_idx]->readPC(),
+ loadQueue[load_idx]->pcState(),
loadQueue[load_idx]->seqNum);
if (isStalled() && load_idx == stallingLoadIdx) {
@@ -906,9 +906,9 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
break;
}
- DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
+ DPRINTF(LSQUnit,"Store Instruction PC %s squashed, "
"idx:%i [sn:%lli]\n",
- storeQueue[store_idx].inst->readPC(),
+ storeQueue[store_idx].inst->pcState(),
store_idx, storeQueue[store_idx].inst->seqNum);
// I don't think this can happen. It should have been cleared
@@ -1156,7 +1156,7 @@ LSQUnit<Impl>::dumpInsts()
int load_idx = loadHead;
while (load_idx != loadTail && loadQueue[load_idx]) {
- cprintf("%#x ", loadQueue[load_idx]->readPC());
+ cprintf("%s ", loadQueue[load_idx]->pcState());
incrLdIdx(load_idx);
}
@@ -1167,7 +1167,7 @@ LSQUnit<Impl>::dumpInsts()
int store_idx = storeHead;
while (store_idx != storeTail && storeQueue[store_idx].inst) {
- cprintf("%#x ", storeQueue[store_idx].inst->readPC());
+ cprintf("%s ", storeQueue[store_idx].inst->pcState());
incrStIdx(store_idx);
}
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh
index 5f5e71624..fdea84ed5 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -171,7 +171,7 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
storeBarrierSN);
producing_store = storeBarrierSN;
} else {
- producing_store = depPred.checkInst(inst->readPC());
+ producing_store = depPred.checkInst(inst->instAddr());
}
MemDepEntryPtr store_entry = NULL;
@@ -191,7 +191,7 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
// are ready.
if (!store_entry) {
DPRINTF(MemDepUnit, "No dependency for inst PC "
- "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
+ "%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
inst_entry->memDepReady = true;
@@ -203,8 +203,8 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
} else {
// Otherwise make the instruction dependent on the store/barrier.
DPRINTF(MemDepUnit, "Adding to dependency list; "
- "inst PC %#x is dependent on [sn:%lli].\n",
- inst->readPC(), producing_store);
+ "inst PC %s is dependent on [sn:%lli].\n",
+ inst->pcState(), producing_store);
if (inst->readyToIssue()) {
inst_entry->regsReady = true;
@@ -224,10 +224,10 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
}
if (inst->isStore()) {
- DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
- inst->readPC(), inst->seqNum);
+ DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
+ inst->pcState(), inst->seqNum);
- depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
+ depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
++insertedStores;
} else if (inst->isLoad()) {
@@ -260,10 +260,10 @@ MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
// Might want to turn this part into an inline function or something.
// It's shared between both insert functions.
if (inst->isStore()) {
- DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
- inst->readPC(), inst->seqNum);
+ DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
+ inst->pcState(), inst->seqNum);
- depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
+ depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
++insertedStores;
} else if (inst->isLoad()) {
@@ -313,8 +313,8 @@ void
MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
{
DPRINTF(MemDepUnit, "Marking registers as ready for "
- "instruction PC %#x [sn:%lli].\n",
- inst->readPC(), inst->seqNum);
+ "instruction PC %s [sn:%lli].\n",
+ inst->pcState(), inst->seqNum);
MemDepEntryPtr inst_entry = findInHash(inst);
@@ -336,8 +336,8 @@ void
MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
{
DPRINTF(MemDepUnit, "Marking non speculative "
- "instruction PC %#x as ready [sn:%lli].\n",
- inst->readPC(), inst->seqNum);
+ "instruction PC %s as ready [sn:%lli].\n",
+ inst->pcState(), inst->seqNum);
MemDepEntryPtr inst_entry = findInHash(inst);
@@ -363,9 +363,8 @@ MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
MemDepEntryPtr inst_entry = findInHash(temp_inst);
- DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
- "[sn:%lli].\n",
- temp_inst->readPC(), temp_inst->seqNum);
+ DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
+ temp_inst->pcState(), temp_inst->seqNum);
moveToReady(inst_entry);
@@ -377,9 +376,8 @@ template <class MemDepPred, class Impl>
void
MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
{
- DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
- "[sn:%lli].\n",
- inst->readPC(), inst->seqNum);
+ DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
+ inst->pcState(), inst->seqNum);
ThreadID tid = inst->threadNumber;
@@ -507,10 +505,10 @@ MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
DynInstPtr &violating_load)
{
DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
- " load: %#x, store: %#x\n", violating_load->readPC(),
- store_inst->readPC());
+ " load: %#x, store: %#x\n", violating_load->instAddr(),
+ store_inst->instAddr());
// Tell the memory dependence unit of the violation.
- depPred.violation(violating_load->readPC(), store_inst->readPC());
+ depPred.violation(violating_load->instAddr(), store_inst->instAddr());
}
template <class MemDepPred, class Impl>
@@ -518,9 +516,9 @@ void
MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
{
DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
- inst->readPC(), inst->seqNum);
+ inst->instAddr(), inst->seqNum);
- depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
+ depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
}
template <class MemDepPred, class Impl>
@@ -559,9 +557,9 @@ MemDepUnit<MemDepPred, Impl>::dumpLists()
int num = 0;
while (inst_list_it != instList[tid].end()) {
- cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
+ cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
"Squashed:%i\n\n",
- num, (*inst_list_it)->readPC(),
+ num, (*inst_list_it)->pcState(),
(*inst_list_it)->seqNum,
(*inst_list_it)->threadNumber,
(*inst_list_it)->isIssued(),
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 7f796c4c8..4b321d099 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -591,15 +591,14 @@ DefaultRename<Impl>::renameInsts(ThreadID tid)
insts_to_rename.pop_front();
if (renameStatus[tid] == Unblocking) {
- DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
- "skidBuffer\n",
- tid, inst->seqNum, inst->readPC());
+ DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
+ "skidBuffer\n", tid, inst->seqNum, inst->pcState());
}
if (inst->isSquashed()) {
- DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
- "squashed, skipping.\n",
- tid, inst->seqNum, inst->readPC());
+ DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
+ "squashed, skipping.\n", tid, inst->seqNum,
+ inst->pcState());
++renameSquashedInsts;
@@ -610,8 +609,7 @@ DefaultRename<Impl>::renameInsts(ThreadID tid)
}
DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
- "PC %#x.\n",
- tid, inst->seqNum, inst->readPC());
+ "PC %s.\n", tid, inst->seqNum, inst->pcState());
// Handle serializeAfter/serializeBefore instructions.
// serializeAfter marks the next instruction as serializeBefore.
@@ -716,8 +714,8 @@ DefaultRename<Impl>::skidInsert(ThreadID tid)
assert(tid == inst->threadNumber);
- DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
- "skidBuffer\n", tid, inst->seqNum, inst->readPC());
+ DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
+ "skidBuffer\n", tid, inst->seqNum, inst->pcState());
++renameSkidInsts;
@@ -731,7 +729,7 @@ DefaultRename<Impl>::skidInsert(ThreadID tid)
for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
{
warn("[tid:%u]: %s [sn:%i].\n", tid,
- (*it)->staticInst->disassemble(inst->readPC()),
+ (*it)->staticInst->disassemble(inst->instAddr()),
(*it)->seqNum);
}
panic("Skidbuffer Exceeded Max Size");
@@ -1287,8 +1285,7 @@ DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
unblock(tid);
DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
- "PC %#x.\n",
- tid, serial_inst->seqNum, serial_inst->readPC());
+ "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
// Put instruction into queue here.
serial_inst->clearSerializeBefore();
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index cf0080b48..37f1c5504 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -204,7 +204,7 @@ ROB<Impl>::insertInst(DynInstPtr &inst)
{
assert(inst);
- DPRINTF(ROB, "Adding inst PC %#x to the ROB.\n", inst->readPC());
+ DPRINTF(ROB, "Adding inst PC %s to the ROB.\n", inst->pcState());
assert(numInstsInROB != numEntries);
@@ -247,7 +247,7 @@ ROB<Impl>::retireHead(ThreadID tid)
assert(head_inst->readyToCommit());
DPRINTF(ROB, "[tid:%u]: Retiring head instruction, "
- "instruction PC %#x,[sn:%lli]\n", tid, head_inst->readPC(),
+ "instruction PC %s, [sn:%lli]\n", tid, head_inst->pcState(),
head_inst->seqNum);
--numInstsInROB;
@@ -338,9 +338,9 @@ ROB<Impl>::doSquash(ThreadID tid)
(*squashIt[tid])->seqNum > squashedSeqNum[tid];
++numSquashed)
{
- DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %#x, seq num %i.\n",
+ DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %s, seq num %i.\n",
(*squashIt[tid])->threadNumber,
- (*squashIt[tid])->readPC(),
+ (*squashIt[tid])->pcState(),
(*squashIt[tid])->seqNum);
// Mark the instruction as squashed, and ready to commit so that
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index b7790cfda..4e559000b 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -172,29 +172,24 @@ class O3ThreadContext : public ThreadContext
virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
- /** Reads this thread's PC. */
- virtual uint64_t readPC()
- { return cpu->readPC(thread->threadId()); }
-
- /** Sets this thread's PC. */
- virtual void setPC(uint64_t val);
-
- /** Reads this thread's next PC. */
- virtual uint64_t readNextPC()
- { return cpu->readNextPC(thread->threadId()); }
+ /** Reads this thread's PC state. */
+ virtual TheISA::PCState pcState()
+ { return cpu->pcState(thread->threadId()); }
- /** Sets this thread's next PC. */
- virtual void setNextPC(uint64_t val);
+ /** Sets this thread's PC state. */
+ virtual void pcState(const TheISA::PCState &val);
- virtual uint64_t readMicroPC()
- { return cpu->readMicroPC(thread->threadId()); }
-
- virtual void setMicroPC(uint64_t val);
+ /** Reads this thread's PC. */
+ virtual Addr instAddr()
+ { return cpu->instAddr(thread->threadId()); }
- virtual uint64_t readNextMicroPC()
- { return cpu->readNextMicroPC(thread->threadId()); }
+ /** Reads this thread's next PC. */
+ virtual Addr nextInstAddr()
+ { return cpu->nextInstAddr(thread->threadId()); }
- virtual void setNextMicroPC(uint64_t val);
+ /** Reads this thread's next PC. */
+ virtual MicroPC microPC()
+ { return cpu->microPC(thread->threadId()); }
/** Reads a miscellaneous register. */
virtual MiscReg readMiscRegNoEffect(int misc_reg)
@@ -247,15 +242,6 @@ class O3ThreadContext : public ThreadContext
}
#endif
- virtual uint64_t readNextNPC()
- {
- return this->cpu->readNextNPC(this->thread->threadId());
- }
-
- virtual void setNextNPC(uint64_t val)
- {
- this->cpu->setNextNPC(val, this->thread->threadId());
- }
};
#endif
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 0b7a2b172..367442830 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -248,11 +248,7 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
// Then finally set the PC, the next PC, the nextNPC, the micropc, and the
// next micropc.
- cpu->setPC(tc->readPC(), tid);
- cpu->setNextPC(tc->readNextPC(), tid);
- cpu->setNextNPC(tc->readNextNPC(), tid);
- cpu->setMicroPC(tc->readMicroPC(), tid);
- cpu->setNextMicroPC(tc->readNextMicroPC(), tid);
+ cpu->pcState(tc->pcState(), tid);
#if !FULL_SYSTEM
this->thread->funcExeInst = tc->readFuncExeInst();
#endif
@@ -327,45 +323,9 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
template <class Impl>
void
-O3ThreadContext<Impl>::setPC(uint64_t val)
+O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
{
- cpu->setPC(val, thread->threadId());
-
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->threadId());
- }
-}
-
-template <class Impl>
-void
-O3ThreadContext<Impl>::setNextPC(uint64_t val)
-{
- cpu->setNextPC(val, thread->threadId());
-
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->threadId());
- }
-}
-
-template <class Impl>
-void
-O3ThreadContext<Impl>::setMicroPC(uint64_t val)
-{
- cpu->setMicroPC(val, thread->threadId());
-
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->threadId());
- }
-}
-
-template <class Impl>
-void
-O3ThreadContext<Impl>::setNextMicroPC(uint64_t val)
-{
- cpu->setNextMicroPC(val, thread->threadId());
+ cpu->pcState(val, thread->threadId());
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-09 10:38:42 +0000