diff options
author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-02-07 10:53:37 -0800 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-02-07 10:53:37 -0800 |
commit | 997fc505a8b2ed843f2c87bd2371e6510f731324 (patch) | |
tree | 5dd0911a77a2f36e6ee2b9dffc9af68783739134 /src/cpu/o3 | |
parent | 23d970e6b91158350c1ef694f26d24851e7c34c5 (diff) | |
download | gem5-997fc505a8b2ed843f2c87bd2371e6510f731324.tar.xz |
Make memory commands dense again to avoid cache stat table explosion.
Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.
--HG--
extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 2 | ||||
-rw-r--r-- | src/cpu/o3/lsq_unit.hh | 5 | ||||
-rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 3 |
3 files changed, 6 insertions, 4 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index b80fc72e1..e6a779823 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -602,7 +602,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid // Build packet here. PacketPtr data_pkt = new Packet(mem_req, - Packet::ReadReq, Packet::Broadcast); + MemCmd::ReadReq, Packet::Broadcast); data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); cacheDataPC[tid] = block_PC; diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 9c7eb7780..2419afe29 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -574,7 +574,8 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx) "addr %#x, data %#x\n", store_idx, req->getVaddr(), data); - PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast); + PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq, + Packet::Broadcast); data_pkt->dataStatic(load_inst->memData); WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); @@ -638,7 +639,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx) // if we the cache is not blocked, do cache access if (!lsq->cacheBlocked()) { PacketPtr data_pkt = - new Packet(req, Packet::ReadReq, Packet::Broadcast); + new Packet(req, MemCmd::ReadReq, Packet::Broadcast); data_pkt->dataStatic(load_inst->memData); LSQSenderState *state = new LSQSenderState; diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index ebd9301f6..3ba22a530 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -613,7 +613,8 @@ LSQUnit<Impl>::writebackStores() (sizeof(TheISA::IntReg) - req->getSize()) : 0), req->getSize()); - PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); + PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq, + Packet::Broadcast); data_pkt->dataStatic(inst->memData); LSQSenderState *state = new LSQSenderState; |