diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-08-01 22:50:14 -0700 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-08-01 22:50:14 -0700 |
commit | a13a706a207296b40dbe43576fad423cf5f4679a (patch) | |
tree | 119bd1bd09542130d603c8f30c0494313180753a /src/cpu/o3 | |
parent | 1c2800465480993040e3058ef94ce30efbe982ec (diff) | |
download | gem5-a13a706a207296b40dbe43576fad423cf5f4679a.tar.xz |
Fix setting of INST_FETCH flag for O3 CPU.
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index a76e07576..3781113bd 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -596,9 +596,9 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid // Setup the memReq to do a read of the first instruction's address. // Set the appropriate read size and flags as well. // Build request here. - RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, - fetch_PC, cpu->thread[tid]->contextId(), - tid); + RequestPtr mem_req = + new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH, + fetch_PC, cpu->thread[tid]->contextId(), tid); memReq[tid] = mem_req; |