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authorGabe Black <gblack@eecs.umich.edu>2007-04-22 17:50:43 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-04-22 17:50:43 +0000
commitacc62514b1a4244182a7e5fad8ca03505389d94d (patch)
tree29e96f23f04f19c16a9fdf1f7ef5fa9d7f23b277 /src/cpu/o3
parentcea543576082ed860e8dae17519ace48e5b2c78a (diff)
downloadgem5-acc62514b1a4244182a7e5fad8ca03505389d94d.tar.xz
Make the floating point zero register special handling only apply for ALPHA.
--HG-- extra : convert_revision : 4f393a5471656b29cecbacfcb337992239775915
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/free_list.hh2
-rw-r--r--src/cpu/o3/regfile.hh4
-rw-r--r--src/cpu/o3/rename_map.cc4
-rw-r--r--src/cpu/o3/scoreboard.cc15
4 files changed, 25 insertions, 0 deletions
diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh
index c669b0b34..42fc0c533 100644
--- a/src/cpu/o3/free_list.hh
+++ b/src/cpu/o3/free_list.hh
@@ -168,7 +168,9 @@ SimpleFreeList::addReg(PhysRegIndex freed_reg)
if (freed_reg != TheISA::ZeroReg)
freeIntRegs.push(freed_reg);
} else if (freed_reg < numPhysicalRegs) {
+#if THE_ISA == ALPHA_ISA
if (freed_reg != (TheISA::ZeroReg + numPhysicalIntRegs))
+#endif
freeFloatRegs.push(freed_reg);
}
}
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index b5b1cd021..75d3fa6eb 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -179,7 +179,9 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
int(reg_idx), (uint64_t)val);
+#if THE_ISA == ALPHA_ISA
if (reg_idx != TheISA::ZeroReg)
+#endif
floatRegFile[reg_idx].d = val;
}
@@ -194,7 +196,9 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
int(reg_idx), (uint64_t)val);
+#if THE_ISA == ALPHA_ISA
if (reg_idx != TheISA::ZeroReg)
+#endif
floatRegFile[reg_idx].d = val;
}
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index b436ec1c3..e6649ce3e 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -165,17 +165,21 @@ SimpleRenameMap::rename(RegIndex arch_reg)
// If it's not referencing the zero register, then rename the
// register.
+#if THE_ISA == ALPHA_ISA
if (arch_reg != floatZeroReg) {
+#endif
renamed_reg = freeList->getFloatReg();
floatRenameMap[arch_reg].physical_reg = renamed_reg;
assert(renamed_reg < numPhysicalRegs &&
renamed_reg >= numPhysicalIntRegs);
+#if THE_ISA == ALPHA_ISA
} else {
// Otherwise return the zero register so nothing bad happens.
renamed_reg = floatZeroReg;
}
+#endif
} else {
// Subtract off the base offset for miscellaneous registers.
arch_reg = arch_reg - numLogicalRegs;
diff --git a/src/cpu/o3/scoreboard.cc b/src/cpu/o3/scoreboard.cc
index 1859b35a4..e7f8b7949 100644
--- a/src/cpu/o3/scoreboard.cc
+++ b/src/cpu/o3/scoreboard.cc
@@ -29,6 +29,7 @@
* Kevin Lim
*/
+#include "arch/isa_specific.hh"
#include "cpu/o3/scoreboard.hh"
Scoreboard::Scoreboard(unsigned activeThreads,
@@ -79,11 +80,18 @@ Scoreboard::name() const
bool
Scoreboard::getReg(PhysRegIndex phys_reg)
{
+#if THE_ISA == ALPHA_ISA
// Always ready if int or fp zero reg.
if (phys_reg == zeroRegIdx ||
phys_reg == (zeroRegIdx + numPhysicalIntRegs)) {
return 1;
}
+#else
+ // Always ready if int zero reg.
+ if (phys_reg == zeroRegIdx) {
+ return 1;
+ }
+#endif
return regScoreBoard[phys_reg];
}
@@ -99,11 +107,18 @@ Scoreboard::setReg(PhysRegIndex phys_reg)
void
Scoreboard::unsetReg(PhysRegIndex ready_reg)
{
+#if THE_ISA == ALPHA_ISA
if (ready_reg == zeroRegIdx ||
ready_reg == (zeroRegIdx + numPhysicalIntRegs)) {
// Don't do anything if int or fp zero reg.
return;
}
+#else
+ if (ready_reg == zeroRegIdx) {
+ // Don't do anything if int zero reg.
+ return;
+ }
+#endif
regScoreBoard[ready_reg] = 0;
}