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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-25 17:37:48 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-01 15:47:55 +0000 |
| commit | b992ecbc5b11c38f9469fe1a02dd1302f97f77c7 (patch) | |
| tree | 3077b9cd638cca96322104b700a1700cfb2524a3 /src/cpu/o3 | |
| parent | 30746da58f3dbcb37df6214999ad48cb7df1cc4a (diff) | |
| download | gem5-b992ecbc5b11c38f9469fe1a02dd1302f97f77c7.tar.xz | |
arch-arm: Implement AArch64 ID regs as bitunions
This patch is implementing the following AArch64 ID registers as
bitunions, so that it is easier to query for feature availability:
- ID_AA64DFR0_EL1
- ID_AA64ISAR0_EL1
- ID_AA64ISAR1_EL1
- ID_AA64MMFR1_EL1
- ID_AA64MMFR2_EL1
- ID_AA64PFR0_EL1
They are updated to the latest Armv8.5 arch release version.
RES0 only ID registers like ID_AA64AFR1_EL1 haven't been added.
Change-Id: Ied037abe3757421bcfc2834d397a8cf9a2b9f0a7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/13067
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/o3')
0 files changed, 0 insertions, 0 deletions