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| author | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:27 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:27 -0700 |
| commit | e0de2c34433be76eac7798e58e1ae02f5bffb732 (patch) | |
| tree | 120f809cf3feb35e6b42e83a9896b8ae673c5445 /src/cpu/o3 | |
| parent | 7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 (diff) | |
| download | gem5-e0de2c34433be76eac7798e58e1ae02f5bffb732.tar.xz | |
tlb: More fixing of unified TLB
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index f9cc78c18..fcee2daa6 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -602,7 +602,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid // Translate the instruction request. fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(), - false, true); + BaseTLB::Execute); // In the case of faults, the fetch stage may need to stall and wait // for the ITB miss to be handled. |