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authorKorey Sewell <ksewell@umich.edu>2007-06-28 05:30:46 -0400
committerKorey Sewell <ksewell@umich.edu>2007-06-28 05:30:46 -0400
commite28cbc98a0c1cc516f8086697f69db702bbe47de (patch)
tree174383e26a8d83ea19d804c4285bfd4f7821b317 /src/cpu/o3
parentac19e0c5050219cbb0579a319fa3fab5cf92835d (diff)
downloadgem5-e28cbc98a0c1cc516f8086697f69db702bbe47de.tar.xz
o3cpu build for mips
--HG-- extra : convert_revision : 2c0be7a8c0a54ba5b1b2b69468f788d20abc8452
Diffstat (limited to 'src/cpu/o3')
-rwxr-xr-xsrc/cpu/o3/mips/dyn_inst.hh54
1 files changed, 52 insertions, 2 deletions
diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index cf78c0941..7cd53413b 100755
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -107,7 +107,7 @@ class MipsDynInst : public BaseDynInst<Impl>
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
- MiscReg readMiscReg(int misc_reg)
+ MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
{
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
}
@@ -122,12 +122,13 @@ class MipsDynInst : public BaseDynInst<Impl>
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
- void setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
{
return this->cpu->setMiscReg(misc_reg, val,
this->threadNumber);
}
+
/** Calls a syscall. */
void syscall(int64_t callnum);
@@ -206,6 +207,55 @@ class MipsDynInst : public BaseDynInst<Impl>
BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
+ /** Reads a miscellaneous register. */
+ TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
+ {
+ return this->cpu->readMiscRegNoEffect(
+ si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+ this->threadNumber);
+ }
+
+ /** Reads a misc. register, including any side-effects the read
+ * might have as defined by the architecture.
+ */
+ TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+ {
+ return this->cpu->readMiscReg(
+ si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+ this->threadNumber);
+ }
+
+ /** Sets a misc. register. */
+ void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
+ {
+ this->instResult.integer = val;
+ return this->cpu->setMiscRegNoEffect(
+ si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+ val, this->threadNumber);
+ }
+
+ /** Sets a misc. register, including any side-effects the write
+ * might have as defined by the architecture.
+ */
+ void setMiscRegOperand(const StaticInst *si, int idx,
+ const MiscReg &val)
+ {
+ return this->cpu->setMiscReg(
+ si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+ val, this->threadNumber);
+ }
+
+ uint64_t readRegOtherThread(int misc_reg)
+ {
+ panic("MIPS MT not defined for O3 CPU.\n");
+ return 0;
+ }
+
+ void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
+ {
+ panic("MIPS MT not defined for O3 CPU.\n");
+ }
+
public:
/** Calculates EA part of a memory instruction. Currently unused,
* though it may be useful in the future if we want to split