mem: Split port retry for all different packet classes

This patch fixes a long-standing isue with the port flow
control. Before this patch the retry mechanism was shared between all
different packet classes. As a result, a snoop response could get
stuck behind a request waiting for a retry, even if the send/recv
functions were split. This caused message-dependent deadlocks in
stress-test scenarios.

The patch splits the retry into one per packet (message) class. Thus,
sendTimingReq has a corresponding recvReqRetry, sendTimingResp has
recvRespRetry etc. Most of the changes to the code involve simply
clarifying what type of request a specific object was accepting.

The biggest change in functionality is in the cache downstream packet
queue, facing the memory. This queue was shared by requests and snoop
responses, and it is now split into two queues, each with their own
flow control, but the same physical MasterPort. These changes fixes
the previously seen deadlocks.

6 files changed, 10 insertions, 10 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 434bfd7da..fc7643be2 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -101,9 +101,9 @@ FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
 
 template<class Impl>
 void
-FullO3CPU<Impl>::IcachePort::recvRetry()
+FullO3CPU<Impl>::IcachePort::recvReqRetry()
 {
-    fetch->recvRetry();
+    fetch->recvReqRetry();
 }
 
 template <class Impl>
@@ -126,9 +126,9 @@ FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::DcachePort::recvRetry()
+FullO3CPU<Impl>::DcachePort::recvReqRetry()
 {
-    lsq->recvRetry();
+    lsq->recvReqRetry();
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 5b33285c4..c4ccd562b 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -150,7 +150,7 @@ class FullO3CPU : public BaseO3CPU
         virtual void recvTimingSnoopReq(PacketPtr pkt) { }
 
         /** Handles doing a retry of a failed fetch. */
-        virtual void recvRetry();
+        virtual void recvReqRetry();
     };
 
     /**
@@ -185,7 +185,7 @@ class FullO3CPU : public BaseO3CPU
         }
 
         /** Handles doing a retry of the previous send. */
-        virtual void recvRetry();
+        virtual void recvReqRetry();
 
         /**
          * As this CPU requires snooping to maintain the load store queue
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 968d94029..536568bc2 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -224,7 +224,7 @@ class DefaultFetch
     void startupStage();
 
     /** Handles retrying the fetch access. */
-    void recvRetry();
+    void recvReqRetry();
 
     /** Processes cache completion event. */
     void processCacheCompletion(PacketPtr pkt);
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index d3b0b3ac5..a462d9251 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1407,7 +1407,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
 
 template<class Impl>
 void
-DefaultFetch<Impl>::recvRetry()
+DefaultFetch<Impl>::recvReqRetry()
 {
     if (retryPkt != NULL) {
         assert(cacheBlocked);
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 5d57bb52b..d726088ef 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -286,7 +286,7 @@ class LSQ {
     /**
      * Retry the previous send that failed.
      */
-    void recvRetry();
+    void recvReqRetry();
 
     /**
      * Handles writing back and completing the load or store that has
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index e0107e36a..06467243d 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -330,7 +330,7 @@ LSQ<Impl>::violation()
 
 template <class Impl>
 void
-LSQ<Impl>::recvRetry()
+LSQ<Impl>::recvReqRetry()
 {
     iewStage->cacheUnblocked();