diff options
author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-02-15 17:40:08 -0500 |
---|---|---|
committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-02-15 17:40:08 -0500 |
commit | 1eec115c31395e2819c073a1859d75eb5933dac2 (patch) | |
tree | 503552557b8a5504bbb9aa9a3515b0bb398a97fc /src/cpu/o3 | |
parent | 1c7aa665bfc678c33cc05829acc52aebb1d2612c (diff) | |
download | gem5-1eec115c31395e2819c073a1859d75eb5933dac2.tar.xz |
cpu: Refactor memory system checks
CPUs need to test that the memory system is in the right mode in two
places, when the CPU is initialized (unless it's switched out) and on
a drainResume(). This led to some code duplication in the CPU
models. This changeset introduces the verifyMemoryMode() method which
is called by BaseCPU::init() if the CPU isn't switched out. The
individual CPU models are responsible for calling this method when
resuming from a drain as this code is CPU model specific.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/cpu.cc | 22 | ||||
-rw-r--r-- | src/cpu/o3/cpu.hh | 2 |
2 files changed, 13 insertions, 11 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 393b9a189..53250d495 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -646,12 +646,6 @@ FullO3CPU<Impl>::init() { BaseCPU::init(); - if (!params()->switched_out && - system->getMemoryMode() != Enums::timing) { - fatal("The O3 CPU requires the memory system to be in " - "'timing' mode.\n"); - } - for (ThreadID tid = 0; tid < numThreads; ++tid) { // Set noSquashFromTC so that the CPU doesn't squash when initially // setting up registers. @@ -1262,11 +1256,7 @@ FullO3CPU<Impl>::drainResume() return; DPRINTF(Drain, "Resuming...\n"); - - if (system->getMemoryMode() != Enums::timing) { - fatal("The O3 CPU requires the memory system to be in " - "'timing' mode.\n"); - } + verifyMemoryMode(); fetch.drainResume(); commit.drainResume(); @@ -1323,6 +1313,16 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) } template <class Impl> +void +FullO3CPU<Impl>::verifyMemoryMode() const +{ + if (system->getMemoryMode() != Enums::timing) { + fatal("The O3 CPU requires the memory system to be in " + "'timing' mode.\n"); + } +} + +template <class Impl> TheISA::MiscReg FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) { diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 5dd0e222d..719d38ef0 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -479,6 +479,8 @@ class FullO3CPU : public BaseO3CPU /** Takes over from another CPU. */ virtual void takeOverFrom(BaseCPU *oldCPU); + void verifyMemoryMode() const; + /** Get the current instruction sequence number, and increment it. */ InstSeqNum getAndIncrementInstSeq() { return globalSeqNum++; } |