Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs.

src/arch/alpha/isa_traits.hh:
    This got changed to the wrong version by accident.
src/cpu/base.cc:
    Fix up progress event to not schedule itself if the interval is set to 0.
src/cpu/base.hh:
    Fix up the CPU Progress Event to not print itself if it's set to 0.  Also remove stats_reset_inst (something I added to m5 but isn't necessary here).
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
    Remove float variable of instResult; it's always held within the double part now.
src/cpu/checker/cpu_impl.hh:
    Use thread and not cpuXC.
src/cpu/o3/alpha/cpu_builder.cc:
src/cpu/o3/checker_builder.cc:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu_builder.cc:
src/python/m5/objects/BaseCPU.py:
    Remove stats_reset_inst.
src/cpu/o3/commit_impl.hh:
src/cpu/ozone/lw_back_end_impl.hh:
    Get TC, not XCProxy.
src/cpu/o3/cpu.cc:
    Switch out updates from the version of m5 I have.  Also remove serialize code that got added twice.
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/thread_state.hh:
    Remove code that was added twice.
src/cpu/o3/lsq_unit.hh:
    Add back in stats that got lost in the merge.
src/cpu/o3/lsq_unit_impl.hh:
    Use proper method to get flags.  Also wake CPU if we're coming back from a cache miss.
src/cpu/o3/thread_context_impl.hh:
src/cpu/o3/thread_state.hh:
    Support profiling.
src/cpu/ozone/cpu.hh:
    Update to use proper typename.
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst_impl.hh:
    Updates for newmem.
src/cpu/ozone/lw_lsq_impl.hh:
    Get flags correctly.
src/cpu/ozone/thread_state.hh:
    Reorder constructor initialization, use tc.
src/sim/pseudo_inst.cc:
    Allow for loading of symbol file.  Be sure to use ThreadContext and not ExecContext.

--HG--
extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94

10 files changed, 28 insertions, 82 deletions

diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index fbf1f342c..ff123a6f7 100644
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -69,7 +69,6 @@ Param<Counter> max_insts_any_thread;
 Param<Counter> max_insts_all_threads;
 Param<Counter> max_loads_any_thread;
 Param<Counter> max_loads_all_threads;
-Param<Counter> stats_reset_inst;
 Param<Tick> progress_interval;
 
 Param<unsigned> cachePorts;
@@ -188,9 +187,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
                     "Terminate when all threads have reached this load"
                     "count",
                     0),
-    INIT_PARAM_DFLT(stats_reset_inst,
-                    "blah",
-                    0),
     INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
 
     INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
@@ -326,7 +322,6 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     params->max_insts_all_threads = max_insts_all_threads;
     params->max_loads_any_thread = max_loads_any_thread;
     params->max_loads_all_threads = max_loads_all_threads;
-    params->stats_reset_inst = stats_reset_inst;
     params->progress_interval = progress_interval;
 
     //
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index ad83ec57a..02c817499 100644
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -64,7 +64,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
     Param<Counter> max_insts_all_threads;
     Param<Counter> max_loads_any_thread;
     Param<Counter> max_loads_all_threads;
-    Param<Counter> stats_reset_inst;
     Param<Tick> progress_interval;
 
 #if FULL_SYSTEM
@@ -97,8 +96,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
                "terminate when any thread reaches this load count"),
     INIT_PARAM(max_loads_all_threads,
                "terminate when all threads have reached this load count"),
-    INIT_PARAM(stats_reset_inst,
-               "blah"),
     INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
 
 #if FULL_SYSTEM
@@ -133,7 +130,6 @@ CREATE_SIM_OBJECT(O3Checker)
     params->max_insts_all_threads = 0;
     params->max_loads_any_thread = 0;
     params->max_loads_all_threads = 0;
-    params->stats_reset_inst = 0;
     params->exitOnError = exitOnError;
     params->updateOnError = updateOnError;
     params->warnOnlyOnLoadError = warnOnlyOnLoadError;
@@ -148,7 +144,6 @@ CREATE_SIM_OBJECT(O3Checker)
     temp = max_insts_all_threads;
     temp = max_loads_any_thread;
     temp = max_loads_all_threads;
-    temp = stats_reset_inst;
     Tick temp2 = progress_interval;
     params->progress_interval = 0;
     temp2++;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 6ae01ae67..c80e4d8c1 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1095,7 +1095,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 //            (cpu->readMiscReg(AlphaISA::IPR_DTB_CM, tid) & 0x18) != 0;
 //        thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
         thread[tid]->profilePC = head_inst->readPC();
-        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getXCProxy(),
+        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
                                                           head_inst->staticInst);
 
         if (node)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 4279df6f7..7386dfadd 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -795,7 +795,6 @@ unsigned int
 FullO3CPU<Impl>::drain(Event *drain_event)
 {
     DPRINTF(O3CPU, "Switching out\n");
-    BaseCPU::switchOut(_sampler);
     drainCount = 0;
     fetch.drain();
     decode.drain();
@@ -852,6 +851,8 @@ FullO3CPU<Impl>::signalDrained()
 
         changeState(SimObject::Drained);
 
+        BaseCPU::switchOut();
+
         if (drainEvent) {
             drainEvent->process();
             drainEvent = NULL;
@@ -878,6 +879,8 @@ FullO3CPU<Impl>::switchOut()
     if (checker)
         checker->switchOut();
 #endif
+    if (tickEvent.scheduled())
+        tickEvent.squash();
 }
 
 template <class Impl>
@@ -935,45 +938,6 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
 }
 
 template <class Impl>
-void
-FullO3CPU<Impl>::serialize(std::ostream &os)
-{
-    BaseCPU::serialize(os);
-    nameOut(os, csprintf("%s.tickEvent", name()));
-    tickEvent.serialize(os);
-
-    // Use SimpleThread's ability to checkpoint to make it easier to
-    // write out the registers.  Also make this static so it doesn't
-    // get instantiated multiple times (causes a panic in statistics).
-    static CPUExecContext temp;
-
-    for (int i = 0; i < thread.size(); i++) {
-        nameOut(os, csprintf("%s.xc.%i", name(), i));
-        temp.copyXC(thread[i]->getXCProxy());
-        temp.serialize(os);
-    }
-}
-
-template <class Impl>
-void
-FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
-{
-    BaseCPU::unserialize(cp, section);
-    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
-
-    // Use SimpleThread's ability to checkpoint to make it easier to
-    // read in the registers.  Also make this static so it doesn't
-    // get instantiated multiple times (causes a panic in statistics).
-    static CPUExecContext temp;
-
-    for (int i = 0; i < thread.size(); i++) {
-        temp.copyXC(thread[i]->getXCProxy());
-        temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
-        thread[i]->getXCProxy()->copyArchRegs(temp.getProxy());
-    }
-}
-
-template <class Impl>
 uint64_t
 FullO3CPU<Impl>::readIntReg(int reg_idx)
 {
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index c82f6dd21..b2baae296 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -906,22 +906,6 @@ DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
 
 template <class Impl>
 void
-DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
-{
-    while (!insts[tid].empty()) {
-        if (insts[tid].front()->isLoad() ||
-            insts[tid].front()->isStore() ) {
-            toRename->iewInfo[tid].dispatchedToLSQ++;
-        }
-
-        toRename->iewInfo[tid].dispatched++;
-
-        insts[tid].pop();
-    }
-}
-
-template <class Impl>
-void
 DefaultIEW<Impl>::wakeCPU()
 {
     cpu->wakeCPU();
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index a1ac5adb8..2bbab71f0 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -167,16 +167,6 @@ LSQ<Impl>::regStats()
 
 template<class Impl>
 void
-LSQ<Impl>::regStats()
-{
-    //Initialize LSQs
-    for (int tid=0; tid < numThreads; tid++) {
-        thread[tid].regStats();
-    }
-}
-
-template<class Impl>
-void
 LSQ<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
 {
     activeThreads = at_ptr;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 8537e9dd7..90d1a3d53 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -410,6 +410,19 @@ class LSQUnit {
     /** Total number of loads forwaded from LSQ stores. */
     Stats::Scalar<> lsqForwLoads;
 
+    /** Total number of loads ignored due to invalid addresses. */
+    Stats::Scalar<> invAddrLoads;
+
+    /** Total number of squashed loads. */
+    Stats::Scalar<> lsqSquashedLoads;
+
+    /** Total number of responses from the memory system that are
+     * ignored due to the instruction already being squashed. */
+    Stats::Scalar<> lsqIgnoredResponses;
+
+    /** Tota number of memory ordering violations. */
+    Stats::Scalar<> lsqMemOrderViolation;
+
     /** Total number of squashed stores. */
     Stats::Scalar<> lsqSquashedStores;
 
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 2922b81bd..98bea74fb 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -416,7 +416,7 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
         // realizes there is activity.
         // Mark it as executed unless it is an uncached load that
         // needs to hit the head of commit.
-        if (!(inst->req->flags & UNCACHEABLE) || inst->isAtCommit()) {
+        if (!(inst->req->getFlags() & UNCACHEABLE) || inst->isAtCommit()) {
             inst->setExecuted();
         }
         iewStage->instToCommit(inst);
@@ -832,6 +832,7 @@ LSQUnit<Impl>::completeStore(int store_idx)
     // A bit conservative because a store completion may not free up entries,
     // but hopefully avoids two store completions in one cycle from making
     // the CPU tick twice.
+    cpu->wakeCPU();
     cpu->activityThisCycle();
 
     if (store_idx == storeHead) {
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index a4546e669..25e1db21c 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -54,7 +54,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::dumpFuncProfile()
 {
-    // Currently not supported
+    thread->dumpFuncProfile();
 }
 #endif
 
@@ -239,12 +239,16 @@ O3ThreadContext<Impl>::readLastSuspend()
 template <class Impl>
 void
 O3ThreadContext<Impl>::profileClear()
-{}
+{
+    thread->profileClear();
+}
 
 template <class Impl>
 void
 O3ThreadContext<Impl>::profileSample()
-{}
+{
+    thread->profileSample();
+}
 #endif
 
 template <class Impl>
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 0247deb52..5fe7bb94d 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -117,7 +117,7 @@ struct O3ThreadState : public ThreadState {
     void dumpFuncProfile()
     {
         std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
-        profile->dump(xcProxy, *os);
+        profile->dump(tc, *os);
     }
 #endif
 };