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| author | Wade Walker <wade.walker@arm.com> | 2011-07-15 11:53:34 -0500 |
|---|---|---|
| committer | Wade Walker <wade.walker@arm.com> | 2011-07-15 11:53:34 -0500 |
| commit | 8870a5820a458ca22cbd4bec60f223a4fe4949e6 (patch) | |
| tree | d0407f485a0bd6c861dd09f86e5a494dc26ed04d /src/cpu/o3 | |
| parent | e6672d1f291e415c6d7e0453dabe8c8b7eb5ddc1 (diff) | |
| download | gem5-8870a5820a458ca22cbd4bec60f223a4fe4949e6.tar.xz | |
ARM: Fix SWP/SWPB undefined instruction behavior
SWP and SWPB now throw an undefined instruction exception if
SCTLR.SW == 0. This also required the MIDR to be changed
slightly so programs can correctly determine that gem5 supports
the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were
deprecated, but not disabled at CPU startup).
Diffstat (limited to 'src/cpu/o3')
0 files changed, 0 insertions, 0 deletions