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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:56 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:56 -0400 |
| commit | ea402970185d5df01dbad2c0f41b8d76d2eb01cd (patch) | |
| tree | ca6670c9db05e67783b34a4a1d099b9500ef2bdd /src/cpu/o3 | |
| parent | bb1d2f39575795f0b369bb3cabb52c9d42a8b1c6 (diff) | |
| download | gem5-ea402970185d5df01dbad2c0f41b8d76d2eb01cd.tar.xz | |
cpu: Move the branch predictor out of the BaseCPU
The branch predictor is guarded by having either the in-order or
out-of-order CPU as one of the available CPU models and therefore
should not be used in the BaseCPU. This patch moves the parameter to
the relevant CPU classes.
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index f46388b4c..e19881248 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -125,7 +125,9 @@ class DerivO3CPU(BaseCPU): smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") - branchPred = BranchPredictor(numThreads = Parent.numThreads) + branchPred = Param.BranchPredictor(BranchPredictor(numThreads = + Parent.numThreads), + "Branch Predictor") needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', "Enable TSO Memory model") |