Merge with head, hopefully the last time for this batch.

28 files changed, 146 insertions, 65 deletions

diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index c3e561cd9..acc7a9056 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -40,11 +40,15 @@ class DerivO3CPU(BaseCPU):
     activity = Param.Unsigned(0, "Initial count")
 
     if buildEnv['USE_CHECKER']:
-        checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
+        # FIXME: Shouldn't need to derefernce Parent.workload
+        #        Somewhere in the param parsing code
+        #        src/python/m5/params.py is and error that
+        #        has trouble converting the workload parameter properly.
+        checker = Param.BaseCPU(O3Checker(workload=Parent.workload[0],
                                           exitOnError=False,
                                           updateOnError=True,
-                                          warnOnlyOnLoadError=False),
-                                "checker")
+                                          warnOnlyOnLoadError=True),
+                                          "checker")
         checker.itb = Parent.itb
         checker.dtb = Parent.dtb
 
diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py
index d0c4ce537..d53e5e527 100644
--- a/src/cpu/o3/O3Checker.py
+++ b/src/cpu/o3/O3Checker.py
@@ -34,7 +34,7 @@ class O3Checker(BaseCPU):
     exitOnError = Param.Bool(False, "Exit on an error")
     updateOnError = Param.Bool(False,
         "Update the checker with the main CPU's state on an error")
-    warnOnlyOnLoadError = Param.Bool(False,
+    warnOnlyOnLoadError = Param.Bool(True,
         "If a load result is incorrect, only print a warning and do not exit")
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
diff --git a/src/cpu/o3/bpred_unit.hh b/src/cpu/o3/bpred_unit.hh
index 84f2dc8c1..8dbba9085 100644
--- a/src/cpu/o3/bpred_unit.hh
+++ b/src/cpu/o3/bpred_unit.hh
@@ -41,7 +41,7 @@
 #include "cpu/pred/tournament.hh"
 #include "cpu/inst_seq.hh"
 
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
 
 /**
  * Basically a wrapper class to hold both the branch predictor
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index b34613f68..72b50d104 100644
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -31,8 +43,8 @@
 #include <string>
 
 #include "cpu/checker/cpu_impl.hh"
-#include "cpu/o3/alpha/dyn_inst.hh"
-#include "cpu/o3/alpha/impl.hh"
+#include "cpu/o3/dyn_inst.hh"
+#include "cpu/o3/impl.hh"
 #include "cpu/inst_seq.hh"
 #include "params/O3Checker.hh"
 #include "sim/process.hh"
@@ -41,16 +53,16 @@
 class MemObject;
 
 template
-class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >;
+class Checker<O3CPUImpl>;
 
 /**
  * Specific non-templated derived class used for SimObject configuration.
  */
-class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >
+class O3Checker : public Checker<O3CPUImpl>
 {
   public:
     O3Checker(Params *p)
-        : Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >(p)
+          : Checker<O3CPUImpl>(p)
     { }
 };
 
@@ -63,7 +75,7 @@ O3CheckerParams::create()
 {
     O3Checker::Params *params = new O3Checker::Params();
     params->name = name;
-    params->numberOfThreads = 1;
+    params->numThreads = numThreads;
     params->max_insts_any_thread = 0;
     params->max_insts_all_threads = 0;
     params->max_loads_any_thread = 0;
@@ -71,10 +83,8 @@ O3CheckerParams::create()
     params->exitOnError = exitOnError;
     params->updateOnError = updateOnError;
     params->warnOnlyOnLoadError = warnOnlyOnLoadError;
-    params->deferRegistration = defer_registration;
-    params->functionTrace = function_trace;
-    params->functionTraceStart = function_trace_start;
     params->clock = clock;
+    params->tracer = tracer;
     // Hack to touch all parameters.  Consider not deriving Checker
     // from BaseCPU..it's not really a CPU in the end.
     Counter temp;
@@ -91,7 +101,8 @@ O3CheckerParams::create()
     params->system = system;
     params->cpu_id = cpu_id;
     params->profile = profile;
-    params->process = workload;
+    params->interrupts = NULL;
+    params->workload = workload;
 
     O3Checker *cpu = new O3Checker(params);
     return cpu;
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index b45d37df9..f35928b08 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -51,10 +51,10 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/timebuf.hh"
 
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
 
 template <class>
-class O3ThreadState;
+struct O3ThreadState;
 
 /**
  * DefaultCommit handles single threaded and SMT commit. Its width is
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index b6a4c0387..edf7e861b 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -725,6 +725,12 @@ DefaultCommit<Impl>::handleInterrupt()
         assert(!thread[0]->inSyscall);
         thread[0]->inSyscall = true;
 
+#if USE_CHECKER
+        if (cpu->checker) {
+            cpu->checker->handlePendingInt();
+        }
+#endif
+
         // CPU will handle interrupt.
         cpu->processInterrupts(interrupt);
 
@@ -769,8 +775,8 @@ void
 DefaultCommit<Impl>::commit()
 {
     if (FullSystem) {
-        // Check for any interrupt that we've already squashed for and start
-        // processing it.
+        // Check for any interrupt that we've already squashed for and
+        // start processing it.
         if (interrupt != NoFault)
             handleInterrupt();
 
@@ -1128,7 +1134,8 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
         head_inst->setCompleted();
 
 #if USE_CHECKER
-        if (cpu->checker && head_inst->isStore()) {
+        if (cpu->checker) {
+            // Need to check the instruction before its fault is processed
             cpu->checker->verify(head_inst);
         }
 #endif
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index ef08c96f4..d16270943 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -65,6 +65,7 @@
 
 #if USE_CHECKER
 #include "cpu/checker/cpu.hh"
+#include "cpu/checker/thread_context.hh"
 #endif
 
 #if THE_ISA == ALPHA_ISA
@@ -72,7 +73,7 @@
 #include "debug/Activity.hh"
 #endif
 
-class BaseCPUParams;
+struct BaseCPUParams;
 
 using namespace TheISA;
 using namespace std;
@@ -265,7 +266,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
 #if USE_CHECKER
     if (params->checker) {
         BaseCPU *temp_checker = params->checker;
-        checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
+        checker = dynamic_cast<Checker<Impl> *>(temp_checker);
         checker->setIcachePort(&icachePort);
         checker->setSystem(params->system);
     } else {
@@ -759,7 +760,8 @@ FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
 
 template <class Impl>
 bool
-FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
+FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
+                                           int delay)
 {
     // Schedule removal of thread data from CPU
     if (delay){
@@ -780,7 +782,7 @@ void
 FullO3CPU<Impl>::suspendContext(ThreadID tid)
 {
     DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
-    bool deallocated = deallocateContext(tid, false, 1);
+    bool deallocated = scheduleDeallocateContext(tid, false, 1);
     // If this was the last thread then unschedule the tick event.
     if ((activeThreads.size() == 1 && !deallocated) ||
         activeThreads.size() == 0)
@@ -797,7 +799,7 @@ FullO3CPU<Impl>::haltContext(ThreadID tid)
 {
     //For now, this is the same as deallocate
     DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
-    deallocateContext(tid, true, 1);
+    scheduleDeallocateContext(tid, true, 1);
 }
 
 template <class Impl>
@@ -1216,7 +1218,7 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
 
     activityRec.reset();
 
-    BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
+    BaseCPU::takeOverFrom(oldCPU);
 
     fetch.takeOverFrom();
     decode.takeOverFrom();
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 165144c1b..94c0a873b 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -78,7 +78,7 @@ class Checkpoint;
 class MemObject;
 class Process;
 
-class BaseCPUParams;
+struct BaseCPUParams;
 
 class BaseO3CPU : public BaseCPU
 {
@@ -400,7 +400,7 @@ class FullO3CPU : public BaseO3CPU
     /** Remove Thread from Active Threads List &&
      *  Possibly Remove Thread Context from CPU.
      */
-    bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
+    bool scheduleDeallocateContext(ThreadID tid, bool remove, int delay = 1);
 
     /** Remove Thread from Active Threads List &&
      *  Remove Thread Context from CPU.
@@ -725,7 +725,7 @@ class FullO3CPU : public BaseO3CPU
      * instruction results at run time.  This can be set to NULL if it
      * is not being used.
      */
-    Checker<DynInstPtr> *checker;
+    Checker<Impl> *checker;
 #endif
 
     /** Pointer to the system. */
diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh
index 482b4b7fc..663831254 100644
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -36,7 +36,7 @@
 #include "base/statistics.hh"
 #include "cpu/timebuf.hh"
 
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
 
 /**
  * DefaultDecode class handles both single threaded and SMT
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 985e92826..60bca1041 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -38,7 +38,9 @@
 #include "params/DerivO3CPU.hh"
 #include "sim/full_system.hh"
 
-using namespace std;
+// clang complains about std::set being overloaded with Packet::set if
+// we open up the entire namespace std
+using std::list;
 
 template<class Impl>
 DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 76a456ee3..ed1e374e8 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2011 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -41,6 +41,7 @@
  */
 
 #include "base/cp_annotate.hh"
+#include "config/use_checker.hh"
 #include "cpu/o3/dyn_inst.hh"
 #include "sim/full_system.hh"
 
@@ -137,6 +138,11 @@ BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
     bool in_syscall = this->thread->inSyscall;
     this->thread->inSyscall = true;
 
+#if USE_CHECKER
+    if (this->isStoreConditional()) {
+       this->reqToVerify->setExtraData(pkt->req->getExtraData());
+    }
+#endif
     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 
     this->thread->inSyscall = in_syscall;
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index f5d275593..b61ae2c7b 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -56,7 +56,7 @@
 #include "mem/port.hh"
 #include "sim/eventq.hh"
 
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
 
 /**
  * DefaultFetch class handles both single threaded and SMT fetch. Its
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 1b82f8a4c..553198980 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -43,6 +43,9 @@
 
 #include <algorithm>
 #include <cstring>
+#include <list>
+#include <map>
+#include <queue>
 
 #include "arch/isa_traits.hh"
 #include "arch/tlb.hh"
@@ -52,7 +55,6 @@
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/base.hh"
-#include "cpu/checker/cpu.hh"
 #include "cpu/o3/fetch.hh"
 #include "cpu/exetrace.hh"
 #include "debug/Activity.hh"
@@ -66,6 +68,10 @@
 #include "sim/full_system.hh"
 #include "sim/system.hh"
 
+#if USE_CHECKER
+#include "cpu/checker/cpu.hh"
+#endif // USE_CHECKER
+
 using namespace std;
 
 template<class Impl>
diff --git a/src/cpu/o3/fu_pool.cc b/src/cpu/o3/fu_pool.cc
index b7c972b09..3f0e46543 100644
--- a/src/cpu/o3/fu_pool.cc
+++ b/src/cpu/o3/fu_pool.cc
@@ -252,7 +252,7 @@ FUPool::switchOut()
 }
 
 void
-FUPool::takeOverFrom()
+FUPool::takeOver()
 {
     for (int i = 0; i < numFU; i++) {
         unitBusy[i] = false;
diff --git a/src/cpu/o3/fu_pool.hh b/src/cpu/o3/fu_pool.hh
index ea4b53e1a..66804b534 100644
--- a/src/cpu/o3/fu_pool.hh
+++ b/src/cpu/o3/fu_pool.hh
@@ -37,7 +37,6 @@
 #include <vector>
 
 #include "cpu/op_class.hh"
-#include "cpu/sched_list.hh"
 #include "params/FUPool.hh"
 #include "sim/sim_object.hh"
 
@@ -162,7 +161,7 @@ class FUPool : public SimObject
     void switchOut();
 
     /** Takes over from another CPU's thread. */
-    void takeOverFrom();
+    void takeOver();
 };
 
 #endif // __CPU_O3_FU_POOL_HH__
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index 0d7e0f68f..adb797525 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -53,7 +53,7 @@
 #include "cpu/timebuf.hh"
 #include "debug/IEW.hh"
 
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
 class FUPool;
 
 /**
@@ -93,9 +93,6 @@ class DefaultIEW
     typedef typename CPUPol::RenameStruct RenameStruct;
     typedef typename CPUPol::IssueStruct IssueStruct;
 
-    friend class Impl::O3CPU;
-    friend class CPUPol::IQ;
-
   public:
     /** Overall IEW stage status. Used to determine if the CPU can
      * deschedule itself due to a lack of activity.
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 92c8875e4..97b41ad9f 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2011 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -48,6 +48,7 @@
 
 #include "arch/utility.hh"
 #include "config/the_isa.hh"
+#include "config/use_checker.hh"
 #include "cpu/o3/fu_pool.hh"
 #include "cpu/o3/iew.hh"
 #include "cpu/timebuf.hh"
@@ -56,6 +57,10 @@
 #include "debug/IEW.hh"
 #include "params/DerivO3CPU.hh"
 
+#if USE_CHECKER
+#include "cpu/checker/cpu.hh"
+#endif // USE_CHECKER
+
 using namespace std;
 
 template<class Impl>
@@ -294,6 +299,13 @@ DefaultIEW<Impl>::initStage()
             ldstQueue.numFreeEntries(tid);
     }
 
+// Initialize the checker's dcache port here
+#if USE_CHECKER
+    if (cpu->checker) {
+        cpu->checker->setDcachePort(cpu->getDcachePort());
+     }
+#endif
+
     cpu->activateStage(O3CPU::IEWIdx);
 }
 
@@ -400,7 +412,7 @@ DefaultIEW<Impl>::takeOverFrom()
 
     instQueue.takeOverFrom();
     ldstQueue.takeOverFrom();
-    fuPool->takeOverFrom();
+    fuPool->takeOver();
 
     initStage();
     cpu->activityThisCycle();
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index eb35fd285..9ceab1525 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -56,7 +56,7 @@
 #include "cpu/timebuf.hh"
 #include "sim/eventq.hh"
 
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
 class FUPool;
 class MemInterface;
 
@@ -93,8 +93,6 @@ class InstructionQueue
     // Typedef of iterator through the list of instructions.
     typedef typename std::list<DynInstPtr>::iterator ListIt;
 
-    friend class Impl::O3CPU;
-
     /** FU completion event class. */
     class FUCompletion : public Event {
       private:
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index b2016cc9c..2c0779a03 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -51,7 +51,9 @@
 #include "params/DerivO3CPU.hh"
 #include "sim/core.hh"
 
-using namespace std;
+// clang complains about std::set being overloaded with Packet::set if
+// we open up the entire namespace std
+using std::list;
 
 template <class Impl>
 InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index db127a2da..b821dd3f9 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -51,7 +51,7 @@
 #include "mem/port.hh"
 #include "sim/sim_object.hh"
 
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
 
 template <class Impl>
 class LSQ {
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 3c1a4eda3..4247c3796 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -51,7 +51,7 @@
 #include "mem/packet.hh"
 #include "mem/port.hh"
 
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
 
 /**
  * Class that implements the actual LQ and SQ for each specific
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index d0db6f6fe..facd88597 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2011 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -45,7 +45,6 @@
 #include "arch/locked_mem.hh"
 #include "base/str.hh"
 #include "config/the_isa.hh"
-#include "config/use_checker.hh"
 #include "cpu/o3/lsq.hh"
 #include "cpu/o3/lsq_unit.hh"
 #include "debug/Activity.hh"
@@ -246,12 +245,6 @@ void
 LSQUnit<Impl>::setDcachePort(Port *dcache_port)
 {
     dcachePort = dcache_port;
-
-#if USE_CHECKER
-    if (cpu->checker) {
-        cpu->checker->setDcachePort(dcachePort);
-    }
-#endif
 }
 
 template<class Impl>
@@ -878,6 +871,11 @@ LSQUnit<Impl>::writebackStores()
                         inst->seqNum);
                 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
                 cpu->schedule(wb, curTick() + 1);
+#if USE_CHECKER
+                // Make sure to set the LLSC data for verification
+                inst->reqToVerify->setExtraData(0);
+                inst->completeAcc(data_pkt);
+#endif
                 completeStore(storeWBIdx);
                 incrStIdx(storeWBIdx);
                 continue;
diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc
index ac0db4784..234a6f9c4 100644
--- a/src/cpu/o3/mem_dep_unit.cc
+++ b/src/cpu/o3/mem_dep_unit.cc
@@ -32,10 +32,6 @@
 #include "cpu/o3/mem_dep_unit_impl.hh"
 #include "cpu/o3/store_set.hh"
 
-// Force instantation of memory dependency unit using store sets and
-// O3CPUImpl.
-template class MemDepUnit<StoreSet, O3CPUImpl>;
-
 #ifdef DEBUG
 template <>
 int
@@ -47,3 +43,7 @@ template <>
 int
 MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_erase = 0;
 #endif
+
+// Force instantation of memory dependency unit using store sets and
+// O3CPUImpl.
+template class MemDepUnit<StoreSet, O3CPUImpl>;
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index 7d00369d3..ce5a62ef8 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -49,7 +49,7 @@ struct SNHash {
     }
 };
 
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
 
 template <class Impl>
 class InstructionQueue;
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index e2472a62d..a5c83dfea 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -37,7 +37,7 @@
 #include "config/the_isa.hh"
 #include "cpu/timebuf.hh"
 
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
 
 /**
  * DefaultRename handles both single threaded and SMT rename. Its
diff --git a/src/cpu/o3/sat_counter.hh b/src/cpu/o3/sat_counter.hh
index 7dd840f31..17ff8546b 100644
--- a/src/cpu/o3/sat_counter.hh
+++ b/src/cpu/o3/sat_counter.hh
@@ -65,7 +65,8 @@ class SatCounter
      * @param initial_val Starting value for each counter.
      */
     SatCounter(unsigned bits, uint8_t initial_val)
-        : initialVal(initialVal), maxVal((1 << bits) - 1), counter(initial_val)
+        : initialVal(initial_val), maxVal((1 << bits) - 1),
+          counter(initial_val)
     {
         // Check to make sure initial value doesn't exceed the max
         // counter value.
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index ffe828c94..c2096fab2 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -32,6 +44,7 @@
 #define __CPU_O3_THREAD_CONTEXT_HH__
 
 #include "config/the_isa.hh"
+#include "config/use_checker.hh"
 #include "cpu/o3/isa_specific.hh"
 #include "cpu/thread_context.hh"
 
@@ -71,6 +84,10 @@ class O3ThreadContext : public ThreadContext
     /** Returns a pointer to the DTB. */
     TheISA::TLB *getDTBPtr() { return cpu->dtb; }
 
+#if USE_CHECKER
+    BaseCPU *getCheckerCpuPtr() { return NULL; }
+#endif
+
     Decoder *getDecoderPtr() { return &cpu->fetch.decoder; }
 
     /** Returns a pointer to this CPU. */
@@ -177,6 +194,10 @@ class O3ThreadContext : public ThreadContext
     /** Sets this thread's PC state. */
     virtual void pcState(const TheISA::PCState &val);
 
+#if USE_CHECKER
+    virtual void pcStateNoRecord(const TheISA::PCState &val);
+#endif
+
     /** Reads this thread's PC. */
     virtual Addr instAddr()
     { return cpu->instAddr(thread->threadId()); }
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 5ba454458..2ea39f3eb 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2011 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -44,6 +44,7 @@
 #include "arch/kernel_stats.hh"
 #include "arch/registers.hh"
 #include "config/the_isa.hh"
+#include "config/use_checker.hh"
 #include "cpu/o3/thread_context.hh"
 #include "cpu/quiesce_event.hh"
 #include "debug/O3CPU.hh"
@@ -296,6 +297,20 @@ O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
     }
 }
 
+#if USE_CHECKER
+template <class Impl>
+void
+O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
+{
+    cpu->pcState(val, thread->threadId());
+
+    // Squash if we're not already in a state update mode.
+    if (!thread->trapPending && !thread->inSyscall) {
+        cpu->squashFromTC(thread->threadId());
+    }
+}
+#endif
+
 template <class Impl>
 int
 O3ThreadContext<Impl>::flattenIntIndex(int reg)