diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-03 04:25:33 -0500 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-03 04:25:33 -0500 |
commit | 118b9dc1f9e84a12ea26743f6cec1eac5b4ab13a (patch) | |
tree | 7eb447e419acb3607d7922453b3713696e05acf4 /src/cpu/o3 | |
parent | c8fc116c7636893517254f785707eba1726d3265 (diff) | |
download | gem5-118b9dc1f9e84a12ea26743f6cec1eac5b4ab13a.tar.xz |
Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however.
--HG--
extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/alpha/cpu.hh | 3 | ||||
-rw-r--r-- | src/cpu/o3/alpha/cpu_impl.hh | 5 | ||||
-rw-r--r-- | src/cpu/o3/alpha/dyn_inst.hh | 2 | ||||
-rw-r--r-- | src/cpu/o3/alpha/dyn_inst_impl.hh | 9 | ||||
-rw-r--r-- | src/cpu/o3/alpha/thread_context.hh | 5 | ||||
-rw-r--r-- | src/cpu/o3/commit_impl.hh | 3 | ||||
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 13 |
7 files changed, 9 insertions, 31 deletions
diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index 01749a2a2..b62550062 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -153,9 +153,6 @@ class AlphaO3CPU : public FullO3CPU<Impl> void post_interrupt(int int_num, int index); /** HW return from error interrupt. */ Fault hwrei(unsigned tid); - /** Returns if a specific PC is a PAL mode PC. */ - bool inPalMode(uint64_t PC) - { return AlphaISA::PcPAL(PC); } bool simPalCheck(int palFunc, unsigned tid); diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 170a53c23..750ccc912 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -278,11 +278,12 @@ AlphaO3CPU<Impl>::processInterrupts() // Check if there are any outstanding interrupts //Handle the interrupts - this->checkInterrupts = false; Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0)); - if (interrupt != NoFault) + if (interrupt != NoFault) { + this->checkInterrupts = false; this->trap(interrupt, 0); + } } #endif // FULL_SYSTEM diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index e711de510..31df8ff78 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -126,8 +126,6 @@ class AlphaDynInst : public BaseDynInst<Impl> #if FULL_SYSTEM /** Calls hardware return from error interrupt. */ Fault hwrei(); - /** Checks if system is in PAL mode. */ - bool inPalMode(); /** Traps to handle specified fault. */ void trap(Fault fault); bool simPalCheck(int palFunc); diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh index f27cd5961..6fc548a85 100644 --- a/src/cpu/o3/alpha/dyn_inst_impl.hh +++ b/src/cpu/o3/alpha/dyn_inst_impl.hh @@ -113,7 +113,7 @@ Fault AlphaDynInst<Impl>::hwrei() { // Can only do a hwrei when in pal mode. - if (!this->cpu->inPalMode(this->readPC())) + if (!(this->readPC() & 0x3)) return new AlphaISA::UnimplementedOpcodeFault; // Set the next PC based on the value of the EXC_ADDR IPR. @@ -128,13 +128,6 @@ AlphaDynInst<Impl>::hwrei() } template <class Impl> -bool -AlphaDynInst<Impl>::inPalMode() -{ - return this->cpu->inPalMode(this->PC); -} - -template <class Impl> void AlphaDynInst<Impl>::trap(Fault fault) { diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh index f0cecee35..bcecb7087 100644 --- a/src/cpu/o3/alpha/thread_context.hh +++ b/src/cpu/o3/alpha/thread_context.hh @@ -47,11 +47,6 @@ class AlphaTC : public O3ThreadContext<Impl> { return this->thread->quiesceEvent; } - - /** Returns if the thread is currently in PAL mode, based on - * the PC's value. */ - virtual bool inPalMode() - { return TheISA::PcPAL(this->cpu->readPC(this->thread->readTid())); } #endif virtual uint64_t readNextNPC() diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index ecf6ed632..bd5c4f9ce 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -638,8 +638,7 @@ DefaultCommit<Impl>::commit() // and no other traps or external squashes are currently pending. // @todo: Allow other threads to handle interrupts. if (cpu->checkInterrupts && - cpu->check_interrupts() && - !cpu->inPalMode(readPC()) && + cpu->check_interrupts(cpu->tcBase(0)) && !trapSquash[0] && !tcSquash[0]) { // Tell fetch that there is an interrupt pending. This will diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 31f3b96d6..4c39341aa 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -559,14 +559,9 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid { Fault fault = NoFault; -#if FULL_SYSTEM - // Flag to say whether or not address is physical addr. - unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0; -#else - unsigned flags = 0; -#endif // FULL_SYSTEM - - if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) { + //AlphaDep + if (cacheBlocked || isSwitchedOut() || + (interruptPending && (fetch_PC & 0x3))) { // Hold off fetch from getting new instructions when: // Cache is blocked, or // while an interrupt is pending and we're not in PAL mode, or @@ -585,7 +580,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid // Setup the memReq to do a read of the first instruction's address. // Set the appropriate read size and flags as well. // Build request here. - RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags, + RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, 0, fetch_PC, cpu->readCpuId(), tid); memReq[tid] = mem_req; |