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| author | Matthias Hille <matthiashille8@gmail.com> | 2017-08-28 22:32:06 +0200 |
|---|---|---|
| committer | Matthias Hille <matthiashille8@gmail.com> | 2017-08-30 09:50:13 +0000 |
| commit | 9f465d0a1b35a37a1c5d3489de0f78f314a662d1 (patch) | |
| tree | 74a031b0d0141d61c96796342a7023a1ff9f93f2 /src/cpu/o3 | |
| parent | 4e939a7b4d33088bda1fe0c2871be2bf61276e21 (diff) | |
| download | gem5-9f465d0a1b35a37a1c5d3489de0f78f314a662d1.tar.xz | |
cpu-o3: fix data pkt initialization for split load
When a split load hits a memory region where IPRs are mapped, the
Writebackevent which is scheduled for that was carrying a data packet
that was not correctly initialized which caused an assertion to fire
when the Writeback event is processed.
Change-Id: I71a4e291f0086f7468d7e8124a0a8f098088972f
Signed-off-by: Matthias Hille <matthiashille8@gmail.com>
Reported-by: Matthias Hille <matthiashille8@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/4620
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 9d885302b..b8e895571 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -610,8 +610,8 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, Cycles delay(0); PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq); + data_pkt->dataStatic(load_inst->memData); if (!TheISA::HasUnalignedMemAcc || !sreqLow) { - data_pkt->dataStatic(load_inst->memData); delay = TheISA::handleIprRead(thread, data_pkt); } else { assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr()); |