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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-06-01 13:44:24 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-06-01 13:44:24 -0400 |
| commit | d8c487c40112590b541dc1e74b435ecb8fe8cef8 (patch) | |
| tree | 8fdd6f4110a6f0ebe7ba9d188541b43aa75478d4 /src/cpu/o3 | |
| parent | 8ab0ffa3dd283b9f710246ba1e3b0c077bd64dc3 (diff) | |
| download | gem5-d8c487c40112590b541dc1e74b435ecb8fe8cef8.tar.xz | |
don't generate trace data unless tracing is on
--HG--
extra : convert_revision : 3953ace8d481d758d6e0d89183c0a7e7bebcf681
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index e16f97558..895b4a46c 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1151,10 +1151,14 @@ DefaultFetch<Impl>::fetch(bool &status_change) DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, instruction->staticInst->disassemble(fetch_PC)); +#if TRACING_ON instruction->traceData = Trace::getInstRecord(curTick, cpu->tcBase(tid), instruction->staticInst, instruction->readPC()); +#elif + instruction->traceData = NULL; +#endif ///FIXME This needs to be more robust in dealing with delay slots #if !ISA_HAS_DELAY_SLOT |