params: Convert the CPU objects to use the auto generated param structs.

A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them.  While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.

42 files changed, 124 insertions, 817 deletions

diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index f0284b2cf..56e537ad2 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -38,10 +38,7 @@ if build_env['USE_CHECKER']:
 class DerivO3CPU(BaseCPU):
     type = 'DerivO3CPU'
     activity = Param.Unsigned(0, "Initial count")
-    numThreads = Param.Unsigned(1, "number of HW thread contexts")
 
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
     if build_env['USE_CHECKER']:
         if not build_env['FULL_SYSTEM']:
             checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
@@ -134,9 +131,6 @@ class DerivO3CPU(BaseCPU):
 
     instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
 
-    function_trace = Param.Bool(False, "Enable function trace")
-    function_trace_start = Param.Tick(0, "Cycle to start function trace")
-
     smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
     smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy")
     smtLSQPolicy    = Param.String('Partitioned', "SMT LSQ Sharing Policy")
diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
index ebc4e7b23..f9f0000d4 100644
--- a/src/cpu/o3/alpha/cpu.hh
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -37,6 +37,7 @@
 #include "cpu/o3/cpu.hh"
 #include "sim/byteswap.hh"
 
+class DerivO3CPUParams;
 class EndQuiesceEvent;
 namespace Kernel {
     class Statistics;
@@ -58,10 +59,9 @@ class AlphaO3CPU : public FullO3CPU<Impl>
   public:
     typedef O3ThreadState<Impl> ImplState;
     typedef O3ThreadState<Impl> Thread;
-    typedef typename Impl::Params Params;
 
     /** Constructs an AlphaO3CPU with the given parameters. */
-    AlphaO3CPU(Params *params);
+    AlphaO3CPU(DerivO3CPUParams *params);
 
     /** Registers statistics. */
     void regStats();
diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index f569c048b..0ff0d5d52 100644
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -34,14 +34,13 @@
 #include "cpu/base.hh"
 #include "cpu/o3/alpha/cpu.hh"
 #include "cpu/o3/alpha/impl.hh"
-#include "cpu/o3/alpha/params.hh"
 #include "cpu/o3/fu_pool.hh"
 #include "params/DerivO3CPU.hh"
 
 class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
 {
   public:
-    DerivO3CPU(AlphaSimpleParams *p)
+    DerivO3CPU(DerivO3CPUParams *p)
         : AlphaO3CPU<AlphaSimpleImpl>(p)
     { }
 };
@@ -49,8 +48,6 @@ class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
 DerivO3CPU *
 DerivO3CPUParams::create()
 {
-    DerivO3CPU *cpu;
-
 #if FULL_SYSTEM
     // Full-system only supports a single thread for the moment.
     int actual_num_threads = 1;
@@ -65,135 +62,18 @@ DerivO3CPUParams::create()
     }
 #endif
 
-    AlphaSimpleParams *params = new AlphaSimpleParams;
-
-    params->clock = clock;
-    params->phase = phase;
-
-    params->tracer = tracer;
-
-    params->name = name;
-    params->numberOfThreads = actual_num_threads;
-    params->cpu_id = cpu_id;
-    params->activity = activity;
-
-    params->itb = itb;
-    params->dtb = dtb;
-
-    params->system = system;
-#if FULL_SYSTEM
-    params->profile = profile;
-
-    params->do_quiesce = do_quiesce;
-    params->do_checkpoint_insts = do_checkpoint_insts;
-    params->do_statistics_insts = do_statistics_insts;
-#else
-    params->workload = workload;
-#endif // FULL_SYSTEM
-
-#if USE_CHECKER
-    params->checker = checker;
-#endif
-
-    params->max_insts_any_thread = max_insts_any_thread;
-    params->max_insts_all_threads = max_insts_all_threads;
-    params->max_loads_any_thread = max_loads_any_thread;
-    params->max_loads_all_threads = max_loads_all_threads;
-    params->progress_interval = progress_interval;
-
-    //
-    // Caches
-    //
-    params->cachePorts = cachePorts;
-
-    params->decodeToFetchDelay = decodeToFetchDelay;
-    params->renameToFetchDelay = renameToFetchDelay;
-    params->iewToFetchDelay = iewToFetchDelay;
-    params->commitToFetchDelay = commitToFetchDelay;
-    params->fetchWidth = fetchWidth;
-
-    params->renameToDecodeDelay = renameToDecodeDelay;
-    params->iewToDecodeDelay = iewToDecodeDelay;
-    params->commitToDecodeDelay = commitToDecodeDelay;
-    params->fetchToDecodeDelay = fetchToDecodeDelay;
-    params->decodeWidth = decodeWidth;
-
-    params->iewToRenameDelay = iewToRenameDelay;
-    params->commitToRenameDelay = commitToRenameDelay;
-    params->decodeToRenameDelay = decodeToRenameDelay;
-    params->renameWidth = renameWidth;
-
-    params->commitToIEWDelay = commitToIEWDelay;
-    params->renameToIEWDelay = renameToIEWDelay;
-    params->issueToExecuteDelay = issueToExecuteDelay;
-    params->dispatchWidth = dispatchWidth;
-    params->issueWidth = issueWidth;
-    params->wbWidth = wbWidth;
-    params->wbDepth = wbDepth;
-    params->fuPool = fuPool;
-
-    params->iewToCommitDelay = iewToCommitDelay;
-    params->renameToROBDelay = renameToROBDelay;
-    params->commitWidth = commitWidth;
-    params->squashWidth = squashWidth;
-    params->trapLatency = trapLatency;
-
-    params->backComSize = backComSize;
-    params->forwardComSize = forwardComSize;
-
-    params->predType = predType;
-    params->localPredictorSize = localPredictorSize;
-    params->localCtrBits = localCtrBits;
-    params->localHistoryTableSize = localHistoryTableSize;
-    params->localHistoryBits = localHistoryBits;
-    params->globalPredictorSize = globalPredictorSize;
-    params->globalCtrBits = globalCtrBits;
-    params->globalHistoryBits = globalHistoryBits;
-    params->choicePredictorSize = choicePredictorSize;
-    params->choiceCtrBits = choiceCtrBits;
-
-    params->BTBEntries = BTBEntries;
-    params->BTBTagSize = BTBTagSize;
-
-    params->RASSize = RASSize;
-
-    params->LQEntries = LQEntries;
-    params->SQEntries = SQEntries;
-
-    params->SSITSize = SSITSize;
-    params->LFSTSize = LFSTSize;
-
-    params->numPhysIntRegs = numPhysIntRegs;
-    params->numPhysFloatRegs = numPhysFloatRegs;
-    params->numIQEntries = numIQEntries;
-    params->numROBEntries = numROBEntries;
-
-    params->smtNumFetchingThreads = smtNumFetchingThreads;
+    numThreads = actual_num_threads;
 
     // Default smtFetchPolicy to "RoundRobin", if necessary.
     std::string round_robin_policy = "RoundRobin";
     std::string single_thread = "SingleThread";
 
     if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
-        params->smtFetchPolicy = round_robin_policy;
+        smtFetchPolicy = round_robin_policy;
     else
-        params->smtFetchPolicy = smtFetchPolicy;
-
-    params->smtIQPolicy    = smtIQPolicy;
-    params->smtLSQPolicy    = smtLSQPolicy;
-    params->smtLSQThreshold = smtLSQThreshold;
-    params->smtROBPolicy   = smtROBPolicy;
-    params->smtROBThreshold = smtROBThreshold;
-    params->smtCommitPolicy = smtCommitPolicy;
-
-    params->instShiftAmt = 2;
-
-    params->deferRegistration = defer_registration;
-
-    params->functionTrace = function_trace;
-    params->functionTraceStart = function_trace_start;
+        smtFetchPolicy = smtFetchPolicy;
 
-    cpu = new DerivO3CPU(params);
+    instShiftAmt = 2;
 
-    return cpu;
+    return new DerivO3CPU(this);
 }
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index 7f8f0547b..dc64113e1 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -40,7 +40,6 @@
 #include "sim/stats.hh"
 
 #include "cpu/o3/alpha/cpu.hh"
-#include "cpu/o3/alpha/params.hh"
 #include "cpu/o3/alpha/thread_context.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/thread_state.hh"
@@ -54,8 +53,11 @@
 #include "sim/system.hh"
 #endif
 
+#include "params/DerivO3CPU.hh"
+
 template <class Impl>
-AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) : FullO3CPU<Impl>(this, params)
+AlphaO3CPU<Impl>::AlphaO3CPU(DerivO3CPUParams *params) :
+    FullO3CPU<Impl>(this, params)
 {
     DPRINTF(O3CPU, "Creating AlphaO3CPU object.\n");
 
diff --git a/src/cpu/o3/alpha/impl.hh b/src/cpu/o3/alpha/impl.hh
index b928ae654..d2d04292c 100644
--- a/src/cpu/o3/alpha/impl.hh
+++ b/src/cpu/o3/alpha/impl.hh
@@ -33,7 +33,6 @@
 
 #include "arch/alpha/isa_traits.hh"
 
-#include "cpu/o3/alpha/params.hh"
 #include "cpu/o3/cpu_policy.hh"
 
 
@@ -77,9 +76,6 @@ struct AlphaSimpleImpl
      */
     typedef O3CPU CPUType;
 
-    /** The Params to be passed to each stage. */
-    typedef AlphaSimpleParams Params;
-
     enum {
       MaxWidth = 8,
       MaxThreads = 4
diff --git a/src/cpu/o3/alpha/params.hh b/src/cpu/o3/alpha/params.hh
deleted file mode 100644
index 164c25312..000000000
--- a/src/cpu/o3/alpha/params.hh
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2004-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#ifndef __CPU_O3_ALPHA_PARAMS_HH__
-#define __CPU_O3_ALPHA_PARAMS_HH__
-
-#include "cpu/o3/cpu.hh"
-#include "cpu/o3/params.hh"
-
-//Forward declarations
-namespace AlphaISA
-{
-    class DTB;
-    class ITB;
-}
-class MemObject;
-class Process;
-class System;
-
-/**
- * This file defines the parameters that will be used for the AlphaO3CPU.
- * This must be defined externally so that the Impl can have a params class
- * defined that it can pass to all of the individual stages.
- */
-
-class AlphaSimpleParams : public O3Params
-{
-  public:
-
-    AlphaISA::ITB *itb;
-    AlphaISA::DTB *dtb;
-};
-
-#endif // __CPU_O3_ALPHA_PARAMS_HH__
diff --git a/src/cpu/o3/bpred_unit.hh b/src/cpu/o3/bpred_unit.hh
index 3c4c8e478..34fe74178 100644
--- a/src/cpu/o3/bpred_unit.hh
+++ b/src/cpu/o3/bpred_unit.hh
@@ -43,6 +43,8 @@
 
 #include <list>
 
+class DerivO3CPUParams;
+
 /**
  * Basically a wrapper class to hold both the branch predictor
  * and the BTB.
@@ -51,7 +53,6 @@ template<class Impl>
 class BPredUnit
 {
   private:
-    typedef typename Impl::Params Params;
     typedef typename Impl::DynInstPtr DynInstPtr;
 
     enum PredType {
@@ -66,7 +67,7 @@ class BPredUnit
     /**
      * @param params The params object, that has the size of the BP and BTB.
      */
-    BPredUnit(Params *params);
+    BPredUnit(DerivO3CPUParams *params);
 
     /**
      * Registers statistics.
diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh
index 84c50b4da..ded72a1b5 100644
--- a/src/cpu/o3/bpred_unit_impl.hh
+++ b/src/cpu/o3/bpred_unit_impl.hh
@@ -34,8 +34,10 @@
 #include "base/traceflags.hh"
 #include "cpu/o3/bpred_unit.hh"
 
+#include "params/DerivO3CPU.hh"
+
 template<class Impl>
-BPredUnit<Impl>::BPredUnit(Params *params)
+BPredUnit<Impl>::BPredUnit(DerivO3CPUParams *params)
   : BTB(params->BTBEntries,
         params->BTBTagSize,
         params->instShiftAmt)
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 80e42fa8b..ff1e517f2 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -37,6 +37,8 @@
 #include "cpu/exetrace.hh"
 #include "cpu/inst_seq.hh"
 
+class DerivO3CPUParams;
+
 template <class>
 class O3ThreadState;
 
@@ -69,7 +71,6 @@ class DefaultCommit
     // Typedefs from the Impl.
     typedef typename Impl::O3CPU O3CPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
-    typedef typename Impl::Params Params;
     typedef typename Impl::CPUPol CPUPol;
 
     typedef typename CPUPol::RenameMap RenameMap;
@@ -136,7 +137,7 @@ class DefaultCommit
 
   public:
     /** Construct a DefaultCommit with the given parameters. */
-    DefaultCommit(O3CPU *_cpu, Params *params);
+    DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
 
     /** Returns the name of the DefaultCommit. */
     std::string name() const;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index ee0f2bb59..86b4da8ce 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -46,6 +46,8 @@
 #include "cpu/checker/cpu.hh"
 #endif
 
+#include "params/DerivO3CPU.hh"
+
 template <class Impl>
 DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
                                           unsigned _tid)
@@ -71,7 +73,7 @@ DefaultCommit<Impl>::TrapEvent::description() const
 }
 
 template <class Impl>
-DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params)
+DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
     : cpu(_cpu),
       squashCounter(0),
       iewToCommitDelay(params->iewToCommitDelay),
@@ -80,7 +82,7 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params)
       fetchToCommitDelay(params->commitToFetchDelay),
       renameWidth(params->renameWidth),
       commitWidth(params->commitWidth),
-      numThreads(params->numberOfThreads),
+      numThreads(params->numThreads),
       drainPending(false),
       switchedOut(false),
       trapLatency(params->trapLatency)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index fac214174..f06aee634 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -52,9 +52,11 @@
 #include "cpu/checker/cpu.hh"
 #endif
 
+class BaseCPUParams;
+
 using namespace TheISA;
 
-BaseO3CPU::BaseO3CPU(Params *params)
+BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
     : BaseCPU(params), cpu_id(0)
 {
 }
@@ -147,7 +149,7 @@ FullO3CPU<Impl>::DeallocateContextEvent::description() const
 }
 
 template <class Impl>
-FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params)
+FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, DerivO3CPUParams *params)
     : BaseO3CPU(params),
       itb(params->itb),
       dtb(params->dtb),
@@ -162,16 +164,16 @@ FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params)
       regFile(o3_cpu, params->numPhysIntRegs,
               params->numPhysFloatRegs),
 
-      freeList(params->numberOfThreads,
+      freeList(params->numThreads,
                TheISA::NumIntRegs, params->numPhysIntRegs,
                TheISA::NumFloatRegs, params->numPhysFloatRegs),
 
       rob(o3_cpu,
           params->numROBEntries, params->squashWidth,
           params->smtROBPolicy, params->smtROBThreshold,
-          params->numberOfThreads),
+          params->numThreads),
 
-      scoreboard(params->numberOfThreads,
+      scoreboard(params->numThreads,
                  TheISA::NumIntRegs, params->numPhysIntRegs,
                  TheISA::NumFloatRegs, params->numPhysFloatRegs,
                  TheISA::NumMiscRegs * number_of_threads,
@@ -192,7 +194,7 @@ FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params)
       physmem(system->physmem),
 #endif // FULL_SYSTEM
       drainCount(0),
-      deferRegistration(params->deferRegistration),
+      deferRegistration(params->defer_registration),
       numThreads(number_of_threads)
 {
     if (!deferRegistration) {
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 61d7dcf22..611d03bad 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -53,6 +53,8 @@
 //#include "cpu/o3/thread_context.hh"
 #include "sim/process.hh"
 
+#include "params/DerivO3CPU.hh"
+
 template <class>
 class Checker;
 class ThreadContext;
@@ -63,13 +65,13 @@ class Checkpoint;
 class MemObject;
 class Process;
 
+class BaseCPUParams;
+
 class BaseO3CPU : public BaseCPU
 {
     //Stuff that's pretty ISA independent will go here.
   public:
-    typedef BaseCPU::Params Params;
-
-    BaseO3CPU(Params *params);
+    BaseO3CPU(BaseCPUParams *params);
 
     void regStats();
 
@@ -96,7 +98,6 @@ class FullO3CPU : public BaseO3CPU
     typedef typename Impl::CPUPol CPUPolicy;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::O3CPU O3CPU;
-    typedef typename Impl::Params Params;
 
     typedef O3ThreadState<Impl> Thread;
 
@@ -256,7 +257,7 @@ class FullO3CPU : public BaseO3CPU
 
   public:
     /** Constructs a CPU with the given parameters. */
-    FullO3CPU(O3CPU *o3_cpu, Params *params);
+    FullO3CPU(O3CPU *o3_cpu, DerivO3CPUParams *params);
     /** Destructor. */
     ~FullO3CPU();
 
diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh
index 3e82033ca..dc8063f29 100644
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -36,6 +36,8 @@
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 
+class DerivO3CPUParams;
+
 /**
  * DefaultDecode class handles both single threaded and SMT
  * decode. Its width is specified by the parameters; each cycles it
@@ -50,7 +52,6 @@ class DefaultDecode
     // Typedefs from the Impl.
     typedef typename Impl::O3CPU O3CPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
-    typedef typename Impl::Params Params;
     typedef typename Impl::CPUPol CPUPol;
 
     // Typedefs from the CPU policy.
@@ -86,7 +87,7 @@ class DefaultDecode
 
   public:
     /** DefaultDecode constructor. */
-    DefaultDecode(O3CPU *_cpu, Params *params);
+    DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params);
 
     /** Returns the name of decode. */
     std::string name() const;
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index ce6738456..015bc8d7f 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -30,15 +30,17 @@
 
 #include "cpu/o3/decode.hh"
 
+#include "params/DerivO3CPU.hh"
+
 template<class Impl>
-DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, Params *params)
+DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
     : cpu(_cpu),
       renameToDecodeDelay(params->renameToDecodeDelay),
       iewToDecodeDelay(params->iewToDecodeDelay),
       commitToDecodeDelay(params->commitToDecodeDelay),
       fetchToDecodeDelay(params->fetchToDecodeDelay),
       decodeWidth(params->decodeWidth),
-      numThreads(params->numberOfThreads)
+      numThreads(params->numThreads)
 {
     _status = Inactive;
 
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index d954bd1e7..f12228ff9 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -41,6 +41,8 @@
 #include "mem/port.hh"
 #include "sim/eventq.hh"
 
+class DerivO3CPUParams;
+
 /**
  * DefaultFetch class handles both single threaded and SMT fetch. Its
  * width is specified by the parameters; each cycle it tries to fetch
@@ -58,7 +60,6 @@ class DefaultFetch
     typedef typename Impl::DynInst DynInst;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::O3CPU O3CPU;
-    typedef typename Impl::Params Params;
 
     /** Typedefs from the CPU policy. */
     typedef typename CPUPol::BPredUnit BPredUnit;
@@ -160,7 +161,7 @@ class DefaultFetch
 
   public:
     /** DefaultFetch constructor. */
-    DefaultFetch(O3CPU *_cpu, Params *params);
+    DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
 
     /** Returns the name of fetch. */
     std::string name() const;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 7d344fa33..0b5ce9380 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -51,6 +51,8 @@
 #include "sim/system.hh"
 #endif // FULL_SYSTEM
 
+#include "params/DerivO3CPU.hh"
+
 template<class Impl>
 void
 DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
@@ -111,7 +113,7 @@ DefaultFetch<Impl>::IcachePort::recvRetry()
 }
 
 template<class Impl>
-DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params)
+DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
     : cpu(_cpu),
       branchPred(params),
       predecoder(NULL),
@@ -123,7 +125,7 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params)
       cacheBlocked(false),
       retryPkt(NULL),
       retryTid(-1),
-      numThreads(params->numberOfThreads),
+      numThreads(params->numThreads),
       numFetchingThreads(params->smtNumFetchingThreads),
       interruptPending(false),
       drainPending(false),
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index 457e2a024..3caf847ed 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -41,6 +41,7 @@
 #include "cpu/o3/scoreboard.hh"
 #include "cpu/o3/lsq.hh"
 
+class DerivO3CPUParams;
 class FUPool;
 
 /**
@@ -70,7 +71,6 @@ class DefaultIEW
     typedef typename Impl::CPUPol CPUPol;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::O3CPU O3CPU;
-    typedef typename Impl::Params Params;
 
     typedef typename CPUPol::IQ IQ;
     typedef typename CPUPol::RenameMap RenameMap;
@@ -115,7 +115,7 @@ class DefaultIEW
 
   public:
     /** Constructs a DefaultIEW with the given parameters. */
-    DefaultIEW(O3CPU *_cpu, Params *params);
+    DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
 
     /** Returns the name of the DefaultIEW stage. */
     std::string name() const;
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 84d10e966..1daecd669 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -37,9 +37,10 @@
 #include "base/timebuf.hh"
 #include "cpu/o3/fu_pool.hh"
 #include "cpu/o3/iew.hh"
+#include "params/DerivO3CPU.hh"
 
 template<class Impl>
-DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, Params *params)
+DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
     : issueToExecQueue(params->backComSize, params->forwardComSize),
       cpu(_cpu),
       instQueue(_cpu, this, params),
@@ -52,7 +53,7 @@ DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, Params *params)
       issueWidth(params->issueWidth),
       wbOutstanding(0),
       wbWidth(params->wbWidth),
-      numThreads(params->numberOfThreads),
+      numThreads(params->numThreads),
       switchedOut(false)
 {
     _status = Active;
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index d0f503977..43da1565d 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -41,8 +41,10 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/dep_graph.hh"
 #include "cpu/op_class.hh"
+#include "sim/eventq.hh"
 #include "sim/host.hh"
 
+class DerivO3CPUParams;
 class FUPool;
 class MemInterface;
 
@@ -70,7 +72,6 @@ class InstructionQueue
     //Typedefs from the Impl.
     typedef typename Impl::O3CPU O3CPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
-    typedef typename Impl::Params Params;
 
     typedef typename Impl::CPUPol::IEW IEW;
     typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
@@ -110,7 +111,7 @@ class InstructionQueue
     };
 
     /** Constructs an IQ. */
-    InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params);
+    InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
 
     /** Destructs the IQ. */
     ~InstructionQueue();
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index fb06f20df..f3ce770fa 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -37,6 +37,8 @@
 #include "enums/OpClass.hh"
 #include "sim/core.hh"
 
+#include "params/DerivO3CPU.hh"
+
 template <class Impl>
 InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
                                                    int fu_idx,
@@ -65,7 +67,7 @@ InstructionQueue<Impl>::FUCompletion::description() const
 
 template <class Impl>
 InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
-                                         Params *params)
+                                         DerivO3CPUParams *params)
     : cpu(cpu_ptr),
       iewStage(iew_ptr),
       fuPool(params->fuPool),
@@ -79,7 +81,7 @@ InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
 
     switchedOut = false;
 
-    numThreads = params->numberOfThreads;
+    numThreads = params->numThreads;
 
     // Set the number of physical registers as the number of int + float
     numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
diff --git a/src/cpu/o3/isa_specific.hh b/src/cpu/o3/isa_specific.hh
index 72a8d4021..9e74f4c8c 100755
--- a/src/cpu/o3/isa_specific.hh
+++ b/src/cpu/o3/isa_specific.hh
@@ -33,17 +33,14 @@
 #if THE_ISA == ALPHA_ISA
     #include "cpu/o3/alpha/cpu.hh"
     #include "cpu/o3/alpha/impl.hh"
-    #include "cpu/o3/alpha/params.hh"
     #include "cpu/o3/alpha/dyn_inst.hh"
 #elif THE_ISA == MIPS_ISA
     #include "cpu/o3/mips/cpu.hh"
     #include "cpu/o3/mips/impl.hh"
-    #include "cpu/o3/mips/params.hh"
     #include "cpu/o3/mips/dyn_inst.hh"
 #elif THE_ISA == SPARC_ISA
     #include "cpu/o3/sparc/cpu.hh"
     #include "cpu/o3/sparc/impl.hh"
-    #include "cpu/o3/sparc/params.hh"
     #include "cpu/o3/sparc/dyn_inst.hh"
 #else
     #error "ISA-specific header files O3CPU not defined ISA"
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 06de608e0..44b69ab40 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -40,10 +40,11 @@
 #include "mem/port.hh"
 #include "sim/sim_object.hh"
 
+class DerivO3CPUParams;
+
 template <class Impl>
 class LSQ {
   public:
-    typedef typename Impl::Params Params;
     typedef typename Impl::O3CPU O3CPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::CPUPol::IEW IEW;
@@ -57,7 +58,7 @@ class LSQ {
     };
 
     /** Constructs an LSQ with the given parameters. */
-    LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params);
+    LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
 
     /** Returns the name of the LSQ. */
     std::string name() const;
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 8ed6f7f54..f8e77b64e 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -34,6 +34,8 @@
 
 #include "cpu/o3/lsq.hh"
 
+#include "params/DerivO3CPU.hh"
+
 template<class Impl>
 void
 LSQ<Impl>::DcachePort::setPeer(Port *port)
@@ -111,11 +113,11 @@ LSQ<Impl>::DcachePort::recvRetry()
 }
 
 template <class Impl>
-LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params)
+LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
     : cpu(cpu_ptr), iewStage(iew_ptr), dcachePort(this),
       LQEntries(params->LQEntries),
       SQEntries(params->SQEntries),
-      numThreads(params->numberOfThreads),
+      numThreads(params->numThreads),
       retryTid(-1)
 {
     dcachePort.snoopRangeSent = false;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 3ae69723d..a82ba3ad5 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -46,6 +46,8 @@
 #include "mem/packet.hh"
 #include "mem/port.hh"
 
+class DerivO3CPUParams;
+
 /**
  * Class that implements the actual LQ and SQ for each specific
  * thread.  Both are circular queues; load entries are freed upon
@@ -63,7 +65,6 @@ class LSQUnit {
   protected:
     typedef TheISA::IntReg IntReg;
   public:
-    typedef typename Impl::Params Params;
     typedef typename Impl::O3CPU O3CPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::CPUPol::IEW IEW;
@@ -75,8 +76,9 @@ class LSQUnit {
     LSQUnit();
 
     /** Initializes the LSQ unit with the specified number of entries. */
-    void init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
-              unsigned maxLQEntries, unsigned maxSQEntries, unsigned id);
+    void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
+            LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
+            unsigned id);
 
     /** Returns the name of the LSQ unit. */
     std::string name() const;
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index e6ff5e931..4b8d693a6 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -112,8 +112,9 @@ LSQUnit<Impl>::LSQUnit()
 
 template<class Impl>
 void
-LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
-                    unsigned maxLQEntries, unsigned maxSQEntries, unsigned id)
+LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
+        LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
+        unsigned id)
 {
     cpu = cpu_ptr;
     iewStage = iew_ptr;
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index a12a3001b..4f66b4599 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -48,6 +48,8 @@ struct SNHash {
     }
 };
 
+class DerivO3CPUParams;
+
 template <class Impl>
 class InstructionQueue;
 
@@ -65,14 +67,13 @@ class InstructionQueue;
 template <class MemDepPred, class Impl>
 class MemDepUnit {
   public:
-    typedef typename Impl::Params Params;
     typedef typename Impl::DynInstPtr DynInstPtr;
 
     /** Empty constructor. Must call init() prior to using in this case. */
     MemDepUnit();
 
     /** Constructs a MemDepUnit with given parameters. */
-    MemDepUnit(Params *params);
+    MemDepUnit(DerivO3CPUParams *params);
 
     /** Frees up any memory allocated. */
     ~MemDepUnit();
@@ -81,7 +82,7 @@ class MemDepUnit {
     std::string name() const;
 
     /** Initializes the unit with parameters and a thread id. */
-    void init(Params *params, int tid);
+    void init(DerivO3CPUParams *params, int tid);
 
     /** Registers statistics. */
     void regStats();
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh
index 64558efaa..124c087f8 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -33,6 +33,8 @@
 #include "cpu/o3/inst_queue.hh"
 #include "cpu/o3/mem_dep_unit.hh"
 
+#include "params/DerivO3CPU.hh"
+
 template <class MemDepPred, class Impl>
 MemDepUnit<MemDepPred, Impl>::MemDepUnit()
     : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
@@ -41,7 +43,7 @@ MemDepUnit<MemDepPred, Impl>::MemDepUnit()
 }
 
 template <class MemDepPred, class Impl>
-MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
+MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
     : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
       loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
 {
@@ -82,7 +84,7 @@ MemDepUnit<MemDepPred, Impl>::name() const
 
 template <class MemDepPred, class Impl>
 void
-MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
+MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, int tid)
 {
     DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
 
diff --git a/src/cpu/o3/mips/cpu.hh b/src/cpu/o3/mips/cpu.hh
index 3724ced46..38eba5aeb 100755
--- a/src/cpu/o3/mips/cpu.hh
+++ b/src/cpu/o3/mips/cpu.hh
@@ -39,6 +39,7 @@
 #include "sim/byteswap.hh"
 #include "sim/faults.hh"
 
+class DerivO3CPUParams;
 class EndQuiesceEvent;
 namespace Kernel {
     class Statistics;
@@ -60,10 +61,9 @@ class MipsO3CPU : public FullO3CPU<Impl>
   public:
     typedef O3ThreadState<Impl> ImplState;
     typedef O3ThreadState<Impl> Thread;
-    typedef typename Impl::Params Params;
 
     /** Constructs an MipsO3CPU with the given parameters. */
-    MipsO3CPU(Params *params);
+    MipsO3CPU(DerivO3CPUParams *params);
 
     /** Registers statistics. */
     void regStats();
diff --git a/src/cpu/o3/mips/cpu_builder.cc b/src/cpu/o3/mips/cpu_builder.cc
index 4690b9804..8fe34afab 100644
--- a/src/cpu/o3/mips/cpu_builder.cc
+++ b/src/cpu/o3/mips/cpu_builder.cc
@@ -35,14 +35,13 @@
 #include "cpu/base.hh"
 #include "cpu/o3/mips/cpu.hh"
 #include "cpu/o3/mips/impl.hh"
-#include "cpu/o3/mips/params.hh"
 #include "cpu/o3/fu_pool.hh"
 #include "params/DerivO3CPU.hh"
 
 class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
 {
   public:
-    DerivO3CPU(MipsSimpleParams *p)
+    DerivO3CPU(DerivO3CPUParams *p)
         : MipsO3CPU<MipsSimpleImpl>(p)
     { }
 };
@@ -50,8 +49,10 @@ class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
 DerivO3CPU *
 DerivO3CPUParams::create()
 {
-    DerivO3CPU *cpu;
-
+#if FULL_SYSTEM
+    // Full-system only supports a single thread for the moment.
+    int actual_num_threads = 1;
+#else
     // In non-full-system mode, we infer the number of threads from
     // the workload if it's not explicitly specified.
     int actual_num_threads =
@@ -60,123 +61,20 @@ DerivO3CPUParams::create()
     if (workload.size() == 0) {
         fatal("Must specify at least one workload!");
     }
-
-    MipsSimpleParams *params = new MipsSimpleParams;
-
-    params->clock = clock;
-    params->phase = phase;
-
-    params->tracer = tracer;
-
-    params->name = name;
-    params->numberOfThreads = actual_num_threads;
-    params->cpu_id = cpu_id;
-    params->activity = activity;
-
-    params->workload = workload;
-
-#if USE_CHECKER
-    params->checker = checker;
 #endif
 
-    params->max_insts_any_thread = max_insts_any_thread;
-    params->max_insts_all_threads = max_insts_all_threads;
-    params->max_loads_any_thread = max_loads_any_thread;
-    params->max_loads_all_threads = max_loads_all_threads;
-
-    //
-    // Caches
-    //
-    params->cachePorts = cachePorts;
-
-    params->decodeToFetchDelay = decodeToFetchDelay;
-    params->renameToFetchDelay = renameToFetchDelay;
-    params->iewToFetchDelay = iewToFetchDelay;
-    params->commitToFetchDelay = commitToFetchDelay;
-    params->fetchWidth = fetchWidth;
-
-    params->renameToDecodeDelay = renameToDecodeDelay;
-    params->iewToDecodeDelay = iewToDecodeDelay;
-    params->commitToDecodeDelay = commitToDecodeDelay;
-    params->fetchToDecodeDelay = fetchToDecodeDelay;
-    params->decodeWidth = decodeWidth;
-
-    params->iewToRenameDelay = iewToRenameDelay;
-    params->commitToRenameDelay = commitToRenameDelay;
-    params->decodeToRenameDelay = decodeToRenameDelay;
-    params->renameWidth = renameWidth;
-
-    params->commitToIEWDelay = commitToIEWDelay;
-    params->renameToIEWDelay = renameToIEWDelay;
-    params->issueToExecuteDelay = issueToExecuteDelay;
-    params->dispatchWidth = dispatchWidth;
-    params->issueWidth = issueWidth;
-    params->wbWidth = wbWidth;
-    params->wbDepth = wbDepth;
-    params->fuPool = fuPool;
-
-    params->iewToCommitDelay = iewToCommitDelay;
-    params->renameToROBDelay = renameToROBDelay;
-    params->commitWidth = commitWidth;
-    params->squashWidth = squashWidth;
-    params->trapLatency = trapLatency;
-
-    params->backComSize = backComSize;
-    params->forwardComSize = forwardComSize;
-
-    params->predType = predType;
-    params->localPredictorSize = localPredictorSize;
-    params->localCtrBits = localCtrBits;
-    params->localHistoryTableSize = localHistoryTableSize;
-    params->localHistoryBits = localHistoryBits;
-    params->globalPredictorSize = globalPredictorSize;
-    params->globalCtrBits = globalCtrBits;
-    params->globalHistoryBits = globalHistoryBits;
-    params->choicePredictorSize = choicePredictorSize;
-    params->choiceCtrBits = choiceCtrBits;
-
-    params->BTBEntries = BTBEntries;
-    params->BTBTagSize = BTBTagSize;
-
-    params->RASSize = RASSize;
-
-    params->LQEntries = LQEntries;
-    params->SQEntries = SQEntries;
-
-    params->SSITSize = SSITSize;
-    params->LFSTSize = LFSTSize;
-
-    params->numPhysIntRegs = numPhysIntRegs;
-    params->numPhysFloatRegs = numPhysFloatRegs;
-    params->numIQEntries = numIQEntries;
-    params->numROBEntries = numROBEntries;
-
-    params->smtNumFetchingThreads = smtNumFetchingThreads;
+    numThreads = actual_num_threads;
 
     // Default smtFetchPolicy to "RoundRobin", if necessary.
     std::string round_robin_policy = "RoundRobin";
     std::string single_thread = "SingleThread";
 
     if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
-        params->smtFetchPolicy = round_robin_policy;
+        smtFetchPolicy = round_robin_policy;
     else
-        params->smtFetchPolicy = smtFetchPolicy;
-
-    params->smtIQPolicy    = smtIQPolicy;
-    params->smtLSQPolicy    = smtLSQPolicy;
-    params->smtLSQThreshold = smtLSQThreshold;
-    params->smtROBPolicy   = smtROBPolicy;
-    params->smtROBThreshold = smtROBThreshold;
-    params->smtCommitPolicy = smtCommitPolicy;
-
-    params->instShiftAmt = 2;
-
-    params->deferRegistration = defer_registration;
-
-    params->functionTrace = function_trace;
-    params->functionTraceStart = function_trace_start;
+        smtFetchPolicy = smtFetchPolicy;
 
-    cpu = new DerivO3CPU(params);
+    instShiftAmt = 2;
 
-    return cpu;
+    return new DerivO3CPU(this);
 }
diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh
index 09d73b4a2..70dbb4ac4 100644
--- a/src/cpu/o3/mips/cpu_impl.hh
+++ b/src/cpu/o3/mips/cpu_impl.hh
@@ -40,13 +40,14 @@
 #include "sim/stats.hh"
 
 #include "cpu/o3/mips/cpu.hh"
-#include "cpu/o3/mips/params.hh"
 #include "cpu/o3/mips/thread_context.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/thread_state.hh"
 
+#include "params/DerivO3CPU.hh"
+
 template <class Impl>
-MipsO3CPU<Impl>::MipsO3CPU(Params *params)
+MipsO3CPU<Impl>::MipsO3CPU(DerivO3CPUParams *params)
     : FullO3CPU<Impl>(this, params)
 {
     DPRINTF(O3CPU, "Creating MipsO3CPU object.\n");
diff --git a/src/cpu/o3/mips/impl.hh b/src/cpu/o3/mips/impl.hh
index ac7181a19..481184006 100644
--- a/src/cpu/o3/mips/impl.hh
+++ b/src/cpu/o3/mips/impl.hh
@@ -34,7 +34,6 @@
 
 #include "arch/mips/isa_traits.hh"
 
-#include "cpu/o3/mips/params.hh"
 #include "cpu/o3/cpu_policy.hh"
 
 
@@ -78,9 +77,6 @@ struct MipsSimpleImpl
      */
     typedef O3CPU CPUType;
 
-    /** The Params to be passed to each stage. */
-    typedef MipsSimpleParams Params;
-
     enum {
       MaxWidth = 8,
       MaxThreads = 4
diff --git a/src/cpu/o3/mips/params.hh b/src/cpu/o3/mips/params.hh
deleted file mode 100644
index 2688d3fb3..000000000
--- a/src/cpu/o3/mips/params.hh
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- *          Korey Sewell
- */
-
-#ifndef __CPU_O3_MIPS_PARAMS_HH__
-#define __CPU_O3_MIPS_PARAMS_HH__
-
-#include "cpu/o3/cpu.hh"
-#include "cpu/o3/params.hh"
-
-//Forward declarations
-namespace MipsISA
-{
-    class MipsDTB;
-    class MipsITB;
-}
-class MemObject;
-class Process;
-class System;
-
-/**
- * This file defines the parameters that will be used for the MipsO3CPU.
- * This must be defined externally so that the Impl can have a params class
- * defined that it can pass to all of the individual stages.
- */
-
-class MipsSimpleParams : public O3Params
-{
-  public:
-    MipsSimpleParams() {}
-
-    //Full System Paramater Objects place here
-    MipsISA::ITB *itb;
-    MipsISA::DTB *dtb;
-};
-
-#endif // __CPU_O3_MIPS_PARAMS_HH__
diff --git a/src/cpu/o3/params.hh b/src/cpu/o3/params.hh
deleted file mode 100755
index b487778c6..000000000
--- a/src/cpu/o3/params.hh
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Copyright (c) 2004-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#ifndef __CPU_O3_PARAMS_HH__
-#define __CPU_O3_PARAMS_HH__
-
-#include "cpu/o3/cpu.hh"
-
-//Forward declarations
-class FUPool;
-
-/**
- * This file defines the parameters that will be used for the O3CPU.
- * This must be defined externally so that the Impl can have a params class
- * defined that it can pass to all of the individual stages.
- */
-class O3Params : public BaseO3CPU::Params
-{
-  public:
-    unsigned activity;
-
-    //
-    // Pointers to key objects
-    //
-#if !FULL_SYSTEM
-    std::vector<Process *> workload;
-    Process *process;
-#endif // FULL_SYSTEM
-
-    BaseCPU *checker;
-
-    //
-    // Caches
-    //
-    //    MemInterface *icacheInterface;
-    //    MemInterface *dcacheInterface;
-
-    unsigned cachePorts;
-
-    //
-    // Fetch
-    //
-    unsigned decodeToFetchDelay;
-    unsigned renameToFetchDelay;
-    unsigned iewToFetchDelay;
-    unsigned commitToFetchDelay;
-    unsigned fetchWidth;
-
-    //
-    // Decode
-    //
-    unsigned renameToDecodeDelay;
-    unsigned iewToDecodeDelay;
-    unsigned commitToDecodeDelay;
-    unsigned fetchToDecodeDelay;
-    unsigned decodeWidth;
-
-    //
-    // Rename
-    //
-    unsigned iewToRenameDelay;
-    unsigned commitToRenameDelay;
-    unsigned decodeToRenameDelay;
-    unsigned renameWidth;
-
-    //
-    // IEW
-    //
-    unsigned commitToIEWDelay;
-    unsigned renameToIEWDelay;
-    unsigned issueToExecuteDelay;
-    unsigned dispatchWidth;
-    unsigned issueWidth;
-    unsigned wbWidth;
-    unsigned wbDepth;
-    FUPool *fuPool;
-
-    //
-    // Commit
-    //
-    unsigned iewToCommitDelay;
-    unsigned renameToROBDelay;
-    unsigned commitWidth;
-    unsigned squashWidth;
-    Tick trapLatency;
-    Tick fetchTrapLatency;
-
-    //
-    // Timebuffer sizes
-    //
-    unsigned backComSize;
-    unsigned forwardComSize;
-
-    //
-    // Branch predictor (BP, BTB, RAS)
-    //
-    std::string predType;
-    unsigned localPredictorSize;
-    unsigned localCtrBits;
-    unsigned localHistoryTableSize;
-    unsigned localHistoryBits;
-    unsigned globalPredictorSize;
-    unsigned globalCtrBits;
-    unsigned globalHistoryBits;
-    unsigned choicePredictorSize;
-    unsigned choiceCtrBits;
-
-    unsigned BTBEntries;
-    unsigned BTBTagSize;
-
-    unsigned RASSize;
-
-    //
-    // Load store queue
-    //
-    unsigned LQEntries;
-    unsigned SQEntries;
-
-    //
-    // Memory dependence
-    //
-    unsigned SSITSize;
-    unsigned LFSTSize;
-
-    //
-    // Miscellaneous
-    //
-    unsigned numPhysIntRegs;
-    unsigned numPhysFloatRegs;
-    unsigned numIQEntries;
-    unsigned numROBEntries;
-
-    //SMT Parameters
-    unsigned smtNumFetchingThreads;
-
-    std::string   smtFetchPolicy;
-
-    std::string   smtIQPolicy;
-    unsigned smtIQThreshold;
-
-    std::string   smtLSQPolicy;
-    unsigned smtLSQThreshold;
-
-    std::string   smtCommitPolicy;
-
-    std::string   smtROBPolicy;
-    unsigned smtROBThreshold;
-
-    // Probably can get this from somewhere.
-    unsigned instShiftAmt;
-};
-
-#endif // __CPU_O3_ALPHA_PARAMS_HH__
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 75d3fa6eb..8bd867136 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -33,6 +33,7 @@
 #define __CPU_O3_REGFILE_HH__
 
 #include "arch/isa_traits.hh"
+#include "arch/regfile.hh"
 #include "arch/types.hh"
 #include "base/trace.hh"
 #include "config/full_system.hh"
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index b2faffe43..c9e0d418d 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -36,6 +36,8 @@
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 
+class DerivO3CPUParams;
+
 /**
  * DefaultRename handles both single threaded and SMT rename. Its
  * width is specified by the parameters; each cycle it tries to rename
@@ -56,7 +58,6 @@ class DefaultRename
     typedef typename Impl::CPUPol CPUPol;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::O3CPU O3CPU;
-    typedef typename Impl::Params Params;
 
     // Typedefs from the CPUPol
     typedef typename CPUPol::DecodeStruct DecodeStruct;
@@ -107,7 +108,7 @@ class DefaultRename
 
   public:
     /** DefaultRename constructor. */
-    DefaultRename(O3CPU *_cpu, Params *params);
+    DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
 
     /** Returns the name of rename. */
     std::string name() const;
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 49c885753..81647b133 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -35,9 +35,10 @@
 #include "arch/regfile.hh"
 #include "config/full_system.hh"
 #include "cpu/o3/rename.hh"
+#include "params/DerivO3CPU.hh"
 
 template <class Impl>
-DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params)
+DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
     : cpu(_cpu),
       iewToRenameDelay(params->iewToRenameDelay),
       decodeToRenameDelay(params->decodeToRenameDelay),
@@ -46,7 +47,7 @@ DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params)
       commitWidth(params->commitWidth),
       resumeSerialize(false),
       resumeUnblocking(false),
-      numThreads(params->numberOfThreads),
+      numThreads(params->numThreads),
       maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
 {
     _status = Inactive;
diff --git a/src/cpu/o3/sparc/cpu.hh b/src/cpu/o3/sparc/cpu.hh
index 3fd193e0f..cccfd7d52 100644
--- a/src/cpu/o3/sparc/cpu.hh
+++ b/src/cpu/o3/sparc/cpu.hh
@@ -37,6 +37,7 @@
 #include "cpu/o3/cpu.hh"
 #include "sim/byteswap.hh"
 
+class DerivO3CPUParams;
 class EndQuiesceEvent;
 namespace Kernel {
     class Statistics;
@@ -58,10 +59,9 @@ class SparcO3CPU : public FullO3CPU<Impl>
   public:
     typedef O3ThreadState<Impl> ImplState;
     typedef O3ThreadState<Impl> Thread;
-    typedef typename Impl::Params Params;
 
     /** Constructs an AlphaO3CPU with the given parameters. */
-    SparcO3CPU(Params *params);
+    SparcO3CPU(DerivO3CPUParams *params);
 
     /** Registers statistics. */
     void regStats();
diff --git a/src/cpu/o3/sparc/cpu_builder.cc b/src/cpu/o3/sparc/cpu_builder.cc
index b08845b4e..c5ea31210 100644
--- a/src/cpu/o3/sparc/cpu_builder.cc
+++ b/src/cpu/o3/sparc/cpu_builder.cc
@@ -35,14 +35,13 @@
 #include "cpu/base.hh"
 #include "cpu/o3/sparc/cpu.hh"
 #include "cpu/o3/sparc/impl.hh"
-#include "cpu/o3/sparc/params.hh"
 #include "cpu/o3/fu_pool.hh"
 #include "params/DerivO3CPU.hh"
 
 class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
 {
   public:
-    DerivO3CPU(SparcSimpleParams *p)
+    DerivO3CPU(DerivO3CPUParams *p)
         : SparcO3CPU<SparcSimpleImpl>(p)
     { }
 };
@@ -50,8 +49,6 @@ class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
 DerivO3CPU *
 DerivO3CPUParams::create()
 {
-    DerivO3CPU *cpu;
-
 #if FULL_SYSTEM
     // Full-system only supports a single thread for the moment.
     int actual_num_threads = 1;
@@ -66,135 +63,18 @@ DerivO3CPUParams::create()
     }
 #endif
 
-    SparcSimpleParams *params = new SparcSimpleParams;
-
-    params->clock = clock;
-    params->phase = phase;
-
-    params->tracer = tracer;
-
-    params->name = name;
-    params->numberOfThreads = actual_num_threads;
-    params->cpu_id = cpu_id;
-    params->activity = activity;
-
-    params->itb = itb;
-    params->dtb = dtb;
-
-    params->system = system;
-#if FULL_SYSTEM
-    params->profile = profile;
-
-    params->do_quiesce = do_quiesce;
-    params->do_checkpoint_insts = do_checkpoint_insts;
-    params->do_statistics_insts = do_statistics_insts;
-#else
-    params->workload = workload;
-#endif // FULL_SYSTEM
-
-#if USE_CHECKER
-    params->checker = checker;
-#endif
-
-    params->max_insts_any_thread = max_insts_any_thread;
-    params->max_insts_all_threads = max_insts_all_threads;
-    params->max_loads_any_thread = max_loads_any_thread;
-    params->max_loads_all_threads = max_loads_all_threads;
-    params->progress_interval = progress_interval;
-
-    //
-    // Caches
-    //
-    params->cachePorts = cachePorts;
-
-    params->decodeToFetchDelay = decodeToFetchDelay;
-    params->renameToFetchDelay = renameToFetchDelay;
-    params->iewToFetchDelay = iewToFetchDelay;
-    params->commitToFetchDelay = commitToFetchDelay;
-    params->fetchWidth = fetchWidth;
-
-    params->renameToDecodeDelay = renameToDecodeDelay;
-    params->iewToDecodeDelay = iewToDecodeDelay;
-    params->commitToDecodeDelay = commitToDecodeDelay;
-    params->fetchToDecodeDelay = fetchToDecodeDelay;
-    params->decodeWidth = decodeWidth;
-
-    params->iewToRenameDelay = iewToRenameDelay;
-    params->commitToRenameDelay = commitToRenameDelay;
-    params->decodeToRenameDelay = decodeToRenameDelay;
-    params->renameWidth = renameWidth;
-
-    params->commitToIEWDelay = commitToIEWDelay;
-    params->renameToIEWDelay = renameToIEWDelay;
-    params->issueToExecuteDelay = issueToExecuteDelay;
-    params->dispatchWidth = dispatchWidth;
-    params->issueWidth = issueWidth;
-    params->wbWidth = wbWidth;
-    params->wbDepth = wbDepth;
-    params->fuPool = fuPool;
-
-    params->iewToCommitDelay = iewToCommitDelay;
-    params->renameToROBDelay = renameToROBDelay;
-    params->commitWidth = commitWidth;
-    params->squashWidth = squashWidth;
-    params->trapLatency = trapLatency;
-
-    params->backComSize = backComSize;
-    params->forwardComSize = forwardComSize;
-
-    params->predType = predType;
-    params->localPredictorSize = localPredictorSize;
-    params->localCtrBits = localCtrBits;
-    params->localHistoryTableSize = localHistoryTableSize;
-    params->localHistoryBits = localHistoryBits;
-    params->globalPredictorSize = globalPredictorSize;
-    params->globalCtrBits = globalCtrBits;
-    params->globalHistoryBits = globalHistoryBits;
-    params->choicePredictorSize = choicePredictorSize;
-    params->choiceCtrBits = choiceCtrBits;
-
-    params->BTBEntries = BTBEntries;
-    params->BTBTagSize = BTBTagSize;
-
-    params->RASSize = RASSize;
-
-    params->LQEntries = LQEntries;
-    params->SQEntries = SQEntries;
-
-    params->SSITSize = SSITSize;
-    params->LFSTSize = LFSTSize;
-
-    params->numPhysIntRegs = numPhysIntRegs;
-    params->numPhysFloatRegs = numPhysFloatRegs;
-    params->numIQEntries = numIQEntries;
-    params->numROBEntries = numROBEntries;
-
-    params->smtNumFetchingThreads = smtNumFetchingThreads;
+    numThreads = actual_num_threads;
 
     // Default smtFetchPolicy to "RoundRobin", if necessary.
     std::string round_robin_policy = "RoundRobin";
     std::string single_thread = "SingleThread";
 
     if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
-        params->smtFetchPolicy = round_robin_policy;
+        smtFetchPolicy = round_robin_policy;
     else
-        params->smtFetchPolicy = smtFetchPolicy;
-
-    params->smtIQPolicy    = smtIQPolicy;
-    params->smtLSQPolicy    = smtLSQPolicy;
-    params->smtLSQThreshold = smtLSQThreshold;
-    params->smtROBPolicy   = smtROBPolicy;
-    params->smtROBThreshold = smtROBThreshold;
-    params->smtCommitPolicy = smtCommitPolicy;
-
-    params->instShiftAmt = 2;
-
-    params->deferRegistration = defer_registration;
-
-    params->functionTrace = function_trace;
-    params->functionTraceStart = function_trace_start;
+        smtFetchPolicy = smtFetchPolicy;
 
-    cpu = new DerivO3CPU(params);
+    instShiftAmt = 2;
 
-    return cpu;
+    return new DerivO3CPU(this);
 }
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh
index 068057fc0..2dd38845f 100644
--- a/src/cpu/o3/sparc/cpu_impl.hh
+++ b/src/cpu/o3/sparc/cpu_impl.hh
@@ -41,7 +41,6 @@
 #include "sim/stats.hh"
 
 #include "cpu/o3/sparc/cpu.hh"
-#include "cpu/o3/sparc/params.hh"
 #include "cpu/o3/sparc/thread_context.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/thread_state.hh"
@@ -54,8 +53,11 @@
 #include "sim/system.hh"
 #endif
 
+#include "params/DerivO3CPU.hh"
+
 template <class Impl>
-SparcO3CPU<Impl>::SparcO3CPU(Params *params) : FullO3CPU<Impl>(this, params)
+SparcO3CPU<Impl>::SparcO3CPU(DerivO3CPUParams *params) :
+    FullO3CPU<Impl>(this, params)
 {
     DPRINTF(O3CPU, "Creating SparcO3CPU object.\n");
 
diff --git a/src/cpu/o3/sparc/impl.hh b/src/cpu/o3/sparc/impl.hh
index 0a970c2f0..982fe36cc 100644
--- a/src/cpu/o3/sparc/impl.hh
+++ b/src/cpu/o3/sparc/impl.hh
@@ -33,7 +33,6 @@
 
 #include "arch/sparc/isa_traits.hh"
 
-#include "cpu/o3/sparc/params.hh"
 #include "cpu/o3/cpu_policy.hh"
 
 
@@ -77,9 +76,6 @@ struct SparcSimpleImpl
      */
     typedef O3CPU CPUType;
 
-    /** The Params to be passed to each stage. */
-    typedef SparcSimpleParams Params;
-
     enum {
       MaxWidth = 8,
       MaxThreads = 4
diff --git a/src/cpu/o3/sparc/params.hh b/src/cpu/o3/sparc/params.hh
deleted file mode 100644
index 09f523818..000000000
--- a/src/cpu/o3/sparc/params.hh
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2004-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __CPU_O3_SPARC_PARAMS_HH__
-#define __CPU_O3_SPARC_PARAMS_HH__
-
-#include "cpu/o3/cpu.hh"
-#include "cpu/o3/params.hh"
-
-//Forward declarations
-namespace SparcISA
-{
-    class DTB;
-    class ITB;
-}
-class MemObject;
-class Process;
-class System;
-
-/**
- * This file defines the parameters that will be used for the AlphaO3CPU.
- * This must be defined externally so that the Impl can have a params class
- * defined that it can pass to all of the individual stages.
- */
-
-class SparcSimpleParams : public O3Params
-{
-  public:
-
-    SparcISA::ITB *itb;
-    SparcISA::DTB *dtb;
-};
-
-#endif // __CPU_O3_SPARC_PARAMS_HH__
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index d8720b3ab..8c634f67e 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -80,8 +80,8 @@ struct O3ThreadState : public ThreadState {
         : ThreadState(_cpu, -1, _thread_num),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
-        if (cpu->params->profile) {
-            profile = new FunctionProfile(cpu->params->system->kernelSymtab);
+        if (cpu->params()->profile) {
+            profile = new FunctionProfile(cpu->params()->system->kernelSymtab);
             Callback *cb =
                 new MakeCallback<O3ThreadState,
                 &O3ThreadState::dumpFuncProfile>(this);