diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-03 13:10:26 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
| commit | 2113b21996d086dab32b9fd388efe3df241bfbd2 (patch) | |
| tree | 26d944027f726dde3ec49b67538663ccc41bcad3 /src/cpu/o3 | |
| parent | 59505f7305cc3f3b7637233fd2d231bd7f561e80 (diff) | |
| download | gem5-2113b21996d086dab32b9fd388efe3df241bfbd2.tar.xz | |
misc: Substitute pointer to Request with aliased RequestPtr
Every usage of Request* in the code has been replaced with the
RequestPtr alias. This is a preparing patch for when RequestPtr will be
the typdefed to a smart pointer to Request rather then a raw pointer to
Request.
Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10995
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 8 | ||||
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index a2813b3dc..a7a095c82 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -510,11 +510,11 @@ class LSQUnit { public: /** Executes the load at the given index. */ - Fault read(Request *req, Request *sreqLow, Request *sreqHigh, + Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, int load_idx); /** Executes the store at the given index. */ - Fault write(Request *req, Request *sreqLow, Request *sreqHigh, + Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, uint8_t *data, int store_idx); /** Returns the index of the head load instruction. */ @@ -549,7 +549,7 @@ class LSQUnit { template <class Impl> Fault -LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, +LSQUnit<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, int load_idx) { DynInstPtr load_inst = loadQueue[load_idx]; @@ -883,7 +883,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, template <class Impl> Fault -LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh, +LSQUnit<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, uint8_t *data, int store_idx) { assert(storeQueue[store_idx].inst); diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index ca6a7f399..e8e2c1853 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -831,7 +831,7 @@ LSQUnit<Impl>::writebackStores() DynInstPtr inst = storeQueue[storeWBIdx].inst; - Request *req = storeQueue[storeWBIdx].req; + RequestPtr req = storeQueue[storeWBIdx].req; RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; |