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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-15 15:16:23 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-15 15:16:23 -0400 |
| commit | 3a5a20769b2ba15905fc2e0a833a8ecbf3098646 (patch) | |
| tree | 599ec2cc9b5dcc6a75ae42d7169d7087f3c8946a /src/cpu/o3 | |
| parent | c6188a226472c23f173b04b0fa86614cf717c9e7 (diff) | |
| download | gem5-3a5a20769b2ba15905fc2e0a833a8ecbf3098646.tar.xz | |
add all the registers we'll need to support for the Intel GbE device and support enough functionality make the driver think
the device is there, and in good working order.
src/dev/SConscript:
add intel gbe to the dev SCons file
src/dev/i8254xGBe.cc:
src/dev/i8254xGBe.hh:
src/dev/i8254xGBe_defs.hh:
use new manner of registers and implement all device registers that are touched through boot and ifup
--HG--
extra : convert_revision : b1a1767f0fd31cd371e432cb48ac9a2e9f9291b5
Diffstat (limited to 'src/cpu/o3')
0 files changed, 0 insertions, 0 deletions