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authorAndreas Hansson <andreas.hansson@arm.com>2012-03-30 09:38:35 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-03-30 09:38:35 -0400
commita14013af3a9e04d68985aea7bcff6c1e70bdbb82 (patch)
tree67e1fcae84daca1bd507d439a24919d178f4d16e /src/cpu/o3
parent390cfc7be9e5e477451a31a1dc8df82b42ee4011 (diff)
downloadgem5-a14013af3a9e04d68985aea7bcff6c1e70bdbb82.tar.xz
CPU: Unify initMemProxies across CPUs and simulation modes
This patch unifies where initMemProxies is called, in the init() method of each BaseCPU subclass, before TheISA::initCPU is called. Moreover, it also ensures that initMemProxies is called in both full-system and syscall-emulation mode, thus unifying also across the modes. An additional check is added in the ThreadState to ensure that initMemProxies is only called once.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/cpu.cc11
1 files changed, 6 insertions, 5 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index f68b500ea..bfc9438d3 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -639,10 +639,13 @@ FullO3CPU<Impl>::init()
{
BaseCPU::init();
- // Set inSyscall so that the CPU doesn't squash when initially
- // setting up registers.
- for (ThreadID tid = 0; tid < numThreads; ++tid)
+ for (ThreadID tid = 0; tid < numThreads; ++tid) {
+ // Set inSyscall so that the CPU doesn't squash when initially
+ // setting up registers.
thread[tid]->inSyscall = true;
+ // Initialise the ThreadContext's memory proxies
+ thread[tid]->initMemProxies(thread[tid]->getTC());
+ }
// this CPU could still be unconnected if we are restoring from a
// checkpoint and this CPU is to be switched in, thus we can only
@@ -655,8 +658,6 @@ FullO3CPU<Impl>::init()
for (ThreadID tid = 0; tid < numThreads; tid++) {
ThreadContext *src_tc = threadContexts[tid];
TheISA::initCPU(src_tc, src_tc->contextId());
- // Initialise the ThreadContext's memory proxies
- thread[tid]->initMemProxies(thread[tid]->getTC());
}
}