mem: track per-request latencies and access depths in the cache hierarchy

Add some values and methods to the request object to track the translation
and access latency for a request and which level of the cache hierarchy responded
to the request.

2 files changed, 3 insertions, 0 deletions

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index b35dd80f3..b121ba707 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -400,6 +400,7 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
         fetchStatus[tid] = IcacheAccessComplete;
     }
 
+    pkt->req->setAccessLatency();
     // Reset the mem req to NULL.
     delete pkt->req;
     delete pkt;
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 77b67ac69..ade076995 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -129,6 +129,8 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
         delete state->mainPkt->req;
         delete state->mainPkt;
     }
+
+    pkt->req->setAccessLatency();
     delete state;
     delete pkt->req;
     delete pkt;