diff options
author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-05-13 12:20:48 -0500 |
---|---|---|
committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-05-13 12:20:48 -0500 |
commit | e3b19cb294c98466a431950888045c6b5d24b675 (patch) | |
tree | 781bcf5ea9fdce45a5747a4d5ef74485ee5e0727 /src/cpu/o3 | |
parent | afbae1ec95e94b6da441a0269dbd9359a7069e3d (diff) | |
download | gem5-e3b19cb294c98466a431950888045c6b5d24b675.tar.xz |
mem: Refactor assignment of Packet types
Put the packet type swizzling (that is currently done in a lot of places)
into a refineCommand() member function.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/lsq_unit.hh | 7 | ||||
-rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 9 |
2 files changed, 6 insertions, 10 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index cb892a4fd..cfb9b8288 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -776,8 +776,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, // if we the cache is not blocked, do cache access bool completedFirst = false; - MemCmd command = req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq; - PacketPtr data_pkt = new Packet(req, command); + PacketPtr data_pkt = Packet::createRead(req); PacketPtr fst_data_pkt = NULL; PacketPtr snd_data_pkt = NULL; @@ -794,8 +793,8 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, fst_data_pkt = data_pkt; } else { // Create the split packets. - fst_data_pkt = new Packet(sreqLow, command); - snd_data_pkt = new Packet(sreqHigh, command); + fst_data_pkt = Packet::createRead(sreqLow); + snd_data_pkt = Packet::createRead(sreqHigh); fst_data_pkt->dataStatic(load_inst->memData); snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize()); diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 90092cf0e..b63a590fb 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -839,9 +839,6 @@ LSQUnit<Impl>::writebackStores() else memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); - MemCmd command = - req->isSwap() ? MemCmd::SwapReq : - (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); PacketPtr data_pkt; PacketPtr snd_data_pkt = NULL; @@ -853,13 +850,13 @@ LSQUnit<Impl>::writebackStores() if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { // Build a single data packet if the store isn't split. - data_pkt = new Packet(req, command); + data_pkt = Packet::createWrite(req); data_pkt->dataStatic(inst->memData); data_pkt->senderState = state; } else { // Create two packets if the store is split in two. - data_pkt = new Packet(sreqLow, command); - snd_data_pkt = new Packet(sreqHigh, command); + data_pkt = Packet::createWrite(sreqLow); + snd_data_pkt = Packet::createWrite(sreqHigh); data_pkt->dataStatic(inst->memData); snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); |