diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-01-27 01:59:20 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-01-27 01:59:20 -0500 |
| commit | 0358ccee23072eef0b6448e3170457037682a452 (patch) | |
| tree | 378b5ba325d74536092a7f245423d81274db38b4 /src/cpu/o3 | |
| parent | e41f54f97f9ebdea32cc6498c346636cddc9e06d (diff) | |
| parent | 5c7bf74c073d0aea808046d10dfcaa6c319217a3 (diff) | |
| download | gem5-0358ccee23072eef0b6448e3170457037682a452.tar.xz | |
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
Hand Merge
--HG--
extra : convert_revision : d5e0c97caebb616493e2f642e915969d7028109c
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/alpha/cpu_impl.hh | 3 | ||||
| -rw-r--r-- | src/cpu/o3/commit_impl.hh | 3 | ||||
| -rw-r--r-- | src/cpu/o3/sparc/cpu_impl.hh | 1 |
3 files changed, 1 insertions, 6 deletions
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index fb0962056..41f149963 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -213,8 +213,6 @@ AlphaO3CPU<Impl>::hwrei(unsigned tid) this->thread[tid]->kernelStats->hwrei(); - this->checkInterrupts = true; - // FIXME: XXX check for interrupts? XXX return NoFault; } @@ -266,7 +264,6 @@ AlphaO3CPU<Impl>::processInterrupts(Fault interrupt) this->interrupts.updateIntrInfo(this->threadContexts[0]); DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); - this->checkInterrupts = false; this->trap(interrupt, 0); } diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 75fe1ed2a..f1457922c 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -672,8 +672,7 @@ DefaultCommit<Impl>::commit() } else { DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); } - } else if (cpu->checkInterrupts && - cpu->check_interrupts(cpu->tcBase(0)) && + } else if (cpu->check_interrupts(cpu->tcBase(0)) && commitStatus[0] != TrapPending && !trapSquash[0] && !tcSquash[0]) { diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index 4a194cbda..c039a8fec 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -241,7 +241,6 @@ SparcO3CPU<Impl>::processInterrupts(Fault interrupt) this->interrupts.updateIntrInfo(this->threadContexts[0]); DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); - this->checkInterrupts = false; this->trap(interrupt, 0); } |