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| author | Lisa Hsu <hsul@eecs.umich.edu> | 2007-01-26 12:51:07 -0500 |
|---|---|---|
| committer | Lisa Hsu <hsul@eecs.umich.edu> | 2007-01-26 12:51:07 -0500 |
| commit | 202d7f62b9ea11e6b72c4b15ff818549ea14f038 (patch) | |
| tree | f5f217121b907fe9cb78243dc35fcc12f17f596e /src/cpu/o3 | |
| parent | 01c959aeaf7f4c6e15bae9d8de227b6d2cbb7ae1 (diff) | |
| download | gem5-202d7f62b9ea11e6b72c4b15ff818549ea14f038.tar.xz | |
eliminate cpu checkInterrupts bool, it is redundant and unnecessary.
--HG--
extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/alpha/cpu_impl.hh | 3 | ||||
| -rw-r--r-- | src/cpu/o3/commit_impl.hh | 3 | ||||
| -rw-r--r-- | src/cpu/o3/sparc/cpu_impl.hh | 1 |
3 files changed, 1 insertions, 6 deletions
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 98fd0699a..980e70fdd 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -217,8 +217,6 @@ AlphaO3CPU<Impl>::hwrei(unsigned tid) this->thread[tid]->kernelStats->hwrei(); - this->checkInterrupts = true; - // FIXME: XXX check for interrupts? XXX return NoFault; } @@ -270,7 +268,6 @@ AlphaO3CPU<Impl>::processInterrupts(Fault interrupt) this->interrupts.updateIntrInfo(this->threadContexts[0]); DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); - this->checkInterrupts = false; this->trap(interrupt, 0); } diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 96f094926..483c2f71b 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -671,8 +671,7 @@ DefaultCommit<Impl>::commit() } else { DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); } - } else if (cpu->checkInterrupts && - cpu->check_interrupts(cpu->tcBase(0)) && + } else if (cpu->check_interrupts(cpu->tcBase(0)) && commitStatus[0] != TrapPending && !trapSquash[0] && !tcSquash[0]) { diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index 536a620bf..66bf7d1c0 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -245,7 +245,6 @@ SparcO3CPU<Impl>::processInterrupts(Fault interrupt) this->interrupts.updateIntrInfo(this->threadContexts[0]); DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); - this->checkInterrupts = false; this->trap(interrupt, 0); } |