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author | Nathanael Premillieu <nathananel.premillieu@arm.com> | 2015-11-22 05:10:19 -0500 |
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committer | Nathanael Premillieu <nathananel.premillieu@arm.com> | 2015-11-22 05:10:19 -0500 |
commit | 488128dab2b9fb728466ade9dd54f9613ee03880 (patch) | |
tree | 4a902c208937c51f52346572ae6b5d6a499fe893 /src/cpu/o3 | |
parent | bbdd7cecb90704cf33277816e18aaf2b8e2ff8c2 (diff) | |
download | gem5-488128dab2b9fb728466ade9dd54f9613ee03880.tar.xz |
cpu: Fix base FP and CC register index in o3 insertThread()
Note that the method is not used, and could possibly be deleted.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/cpu.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index c17b7a9dc..665654f68 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -790,8 +790,8 @@ FullO3CPU<Impl>::insertThread(ThreadID tid) } //Bind Float Regs to Rename Map - int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs; - for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) { + int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs; + for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) { PhysRegIndex phys_reg = freeList.getFloatReg(); renameMap[tid].setEntry(freg,phys_reg); @@ -799,8 +799,8 @@ FullO3CPU<Impl>::insertThread(ThreadID tid) } //Bind condition-code Regs to Rename Map - max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs; - for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; + max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs; + for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) { PhysRegIndex phys_reg = freeList.getCCReg(); |