diff options
author | Sean Wilson <spwilson2@wisc.edu> | 2017-06-28 08:52:08 -0500 |
---|---|---|
committer | Sean Wilson <spwilson2@wisc.edu> | 2017-07-12 20:07:05 +0000 |
commit | 8c1ea47b3c2fc90378eb16f3ad92d4ae522567c5 (patch) | |
tree | 4ac53d611aaedd5728e9f1100d43d166634ab5a8 /src/cpu/o3 | |
parent | 741261f10bb308cdc200c5dfd8eb68567349cf19 (diff) | |
download | gem5-8c1ea47b3c2fc90378eb16f3ad92d4ae522567c5.tar.xz |
cpu: Refactor some Event subclasses to lambdas
Change-Id: If765c6100d67556f157e4e61aa33c2b7eeb8d2f0
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3923
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/commit.hh | 18 | ||||
-rw-r--r-- | src/cpu/o3/commit_impl.hh | 22 | ||||
-rw-r--r-- | src/cpu/o3/cpu.cc | 23 | ||||
-rw-r--r-- | src/cpu/o3/cpu.hh | 18 |
4 files changed, 11 insertions, 70 deletions
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 5977f94f3..f508a372e 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -101,21 +101,6 @@ class DefaultCommit typedef O3ThreadState<Impl> Thread; - /** Event class used to schedule a squash due to a trap (fault or - * interrupt) to happen on a specific cycle. - */ - class TrapEvent : public Event { - private: - DefaultCommit<Impl> *commit; - ThreadID tid; - - public: - TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid); - - void process(); - const char *description() const; - }; - /** Overall commit status. Used to determine if the CPU can deschedule * itself due to a lack of activity. */ @@ -157,6 +142,9 @@ class DefaultCommit /** To probe when an instruction is squashed */ ProbePointArg<DynInstPtr> *ppSquash; + /** Mark the thread as processing a trap. */ + void processTrapEvent(ThreadID tid); + public: /** Construct a DefaultCommit with the given parameters. */ DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index aba2696c2..bf5ee8a38 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -71,26 +71,12 @@ using namespace std; template <class Impl> -DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, - ThreadID _tid) - : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) -{ -} - -template <class Impl> void -DefaultCommit<Impl>::TrapEvent::process() +DefaultCommit<Impl>::processTrapEvent(ThreadID tid) { // This will get reset by commit if it was switched out at the // time of this event processing. - commit->trapSquash[tid] = true; -} - -template <class Impl> -const char * -DefaultCommit<Impl>::TrapEvent::description() const -{ - return "Trap"; + trapSquash[tid] = true; } template <class Impl> @@ -537,7 +523,9 @@ DefaultCommit<Impl>::generateTrapEvent(ThreadID tid, Fault inst_fault) { DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); - TrapEvent *trap = new TrapEvent(this, tid); + EventFunctionWrapper *trap = new EventFunctionWrapper( + [this, tid]{ processTrapEvent(tid); }, + "Trap", true, Event::CPU_Tick_Pri); Cycles latency = dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ? cpu->syscallRetryLatency : trapLatency; diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index c249d90ba..09790f4ce 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -137,31 +137,12 @@ FullO3CPU<Impl>::DcachePort::recvReqRetry() } template <class Impl> -FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) - : Event(CPU_Tick_Pri), cpu(c) -{ -} - -template <class Impl> -void -FullO3CPU<Impl>::TickEvent::process() -{ - cpu->tick(); -} - -template <class Impl> -const char * -FullO3CPU<Impl>::TickEvent::description() const -{ - return "FullO3CPU tick"; -} - -template <class Impl> FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) : BaseO3CPU(params), itb(params->itb), dtb(params->dtb), - tickEvent(this), + tickEvent([this]{ tick(); }, "FullO3CPU tick", + false, Event::CPU_Tick_Pri), #ifndef NDEBUG instcount(0), #endif diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index d78d1b9d3..28ccd15b0 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -199,24 +199,8 @@ class FullO3CPU : public BaseO3CPU virtual bool isSnooping() const { return true; } }; - class TickEvent : public Event - { - private: - /** Pointer to the CPU. */ - FullO3CPU<Impl> *cpu; - - public: - /** Constructs a tick event. */ - TickEvent(FullO3CPU<Impl> *c); - - /** Processes a tick event, calling tick() on the CPU. */ - void process(); - /** Returns the description of the tick event. */ - const char *description() const; - }; - /** The tick event used for scheduling CPU ticks. */ - TickEvent tickEvent; + EventFunctionWrapper tickEvent; /** Schedule tick event, regardless of its current state. */ void scheduleTickEvent(Cycles delay) |