O3CPU: Fix thread writeback logic.

Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.

3 files changed, 13 insertions, 13 deletions

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 86b4da8ce..b16955691 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -814,7 +814,7 @@ DefaultCommit<Impl>::commit()
         // @todo: Make this handle multi-cycle communication between
         // commit and IEW.
         if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
-            !iewStage->hasStoresToWB() && !committedStores[tid]) {
+            !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
             checkEmptyROB[tid] = false;
             toIEW->commitInfo[tid].usedROB = true;
             toIEW->commitInfo[tid].emptyROB = true;
@@ -968,7 +968,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
                     "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
                     head_inst->seqNum, head_inst->readPC());
 
-            if (inst_num > 0 || iewStage->hasStoresToWB()) {
+            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
                 return false;
             }
@@ -983,7 +983,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 
             return false;
         } else if (head_inst->isLoad()) {
-            if (inst_num > 0 || iewStage->hasStoresToWB()) {
+            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
                 return false;
             }
@@ -1038,7 +1038,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
         DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
                 head_inst->seqNum, head_inst->readPC());
 
-        if (iewStage->hasStoresToWB() || inst_num > 0) {
+        if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
             DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
             return false;
         }
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index 3caf847ed..bc60f401b 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -208,6 +208,9 @@ class DefaultIEW
     /** Returns if the LSQ has any stores to writeback. */
     bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
 
+    /** Returns if the LSQ has any stores to writeback. */
+    bool hasStoresToWB(unsigned tid) { return ldstQueue.hasStoresToWB(tid); }
+
     void incrWb(InstSeqNum &sn)
     {
         if (++wbOutstanding == wbMax)
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index f8e77b64e..5aea020a9 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -584,17 +584,14 @@ LSQ<Impl>::hasStoresToWB()
     std::list<unsigned>::iterator threads = activeThreads->begin();
     std::list<unsigned>::iterator end = activeThreads->end();
 
-    if (threads == end)
-        return false;
-
     while (threads != end) {
         unsigned tid = *threads++;
 
-        if (!hasStoresToWB(tid))
-            return false;
+        if (hasStoresToWB(tid))
+            return true;
     }
 
-    return true;
+    return false;
 }
 
 template<class Impl>
@@ -607,11 +604,11 @@ LSQ<Impl>::willWB()
     while (threads != end) {
         unsigned tid = *threads++;
 
-        if (!willWB(tid))
-            return false;
+        if (willWB(tid))
+            return true;
     }
 
-    return true;
+    return false;
 }
 
 template<class Impl>