Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.

src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
    Change ExecContext to ThreadContext.

--HG--
rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh
extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e

10 files changed, 158 insertions, 159 deletions

diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh
index 3c16c3b2e..588b11724 100644
--- a/src/cpu/o3/alpha_cpu.hh
+++ b/src/cpu/o3/alpha_cpu.hh
@@ -32,7 +32,7 @@
 #define __CPU_O3_ALPHA_FULL_CPU_HH__
 
 #include "arch/isa_traits.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/o3/cpu.hh"
 #include "sim/byteswap.hh"
 
@@ -71,20 +71,20 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     AlphaFullCPU(Params *params);
 
     /**
-     * Derived ExecContext class for use with the AlphaFullCPU.  It
+     * Derived ThreadContext class for use with the AlphaFullCPU.  It
      * provides the interface for any external objects to access a
      * single thread's state and some general CPU state.  Any time
      * external objects try to update state through this interface,
      * the CPU will create an event to squash all in-flight
      * instructions in order to ensure state is maintained correctly.
      */
-    class AlphaXC : public ExecContext
+    class AlphaTC : public ThreadContext
     {
       public:
         /** Pointer to the CPU. */
         AlphaFullCPU<Impl> *cpu;
 
-        /** Pointer to the thread state that this XC corrseponds to. */
+        /** Pointer to the thread state that this TC corrseponds to. */
         O3ThreadState<Impl> *thread;
 
         /** Returns a pointer to this CPU. */
@@ -145,9 +145,9 @@ class AlphaFullCPU : public FullO3CPU<Impl>
         virtual void dumpFuncProfile();
 #endif
         /** Takes over execution of a thread from another CPU. */
-        virtual void takeOverFrom(ExecContext *old_context);
+        virtual void takeOverFrom(ThreadContext *old_context);
 
-        /** Registers statistics associated with this XC. */
+        /** Registers statistics associated with this TC. */
         virtual void regStats(const std::string &name);
 
         /** Serializes state. */
@@ -177,8 +177,8 @@ class AlphaFullCPU : public FullO3CPU<Impl>
          */
         virtual TheISA::MachInst getInst();
 
-        /** Copies the architectural registers from another XC into this XC. */
-        virtual void copyArchRegs(ExecContext *xc);
+        /** Copies the architectural registers from another TC into this TC. */
+        virtual void copyArchRegs(ThreadContext *tc);
 
         /** Resets all architectural registers to 0. */
         virtual void clearArchRegs();
@@ -359,9 +359,9 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 
     /** Initiates a squash of all in-flight instructions for a given
      * thread.  The source of the squash is an external update of
-     * state through the XC.
+     * state through the TC.
      */
-    void squashFromXC(unsigned tid);
+    void squashFromTC(unsigned tid);
 
 #if FULL_SYSTEM
     /** Posts an interrupt. */
diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha_cpu_impl.hh
index 7c136638d..7f3d91640 100644
--- a/src/cpu/o3/alpha_cpu_impl.hh
+++ b/src/cpu/o3/alpha_cpu_impl.hh
@@ -68,7 +68,7 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
         // SMT is not supported in FS mode yet.
         assert(this->numThreads == 1);
         this->thread[i] = new Thread(this, 0, params->mem);
-        this->thread[i]->setStatus(ExecContext::Suspended);
+        this->thread[i]->setStatus(ThreadContext::Suspended);
 #else
         if (i < params->workload.size()) {
             DPRINTF(FullCPU, "FullCPU: Workload[%i] process is %#x",
@@ -76,11 +76,11 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
             this->thread[i] = new Thread(this, i, params->workload[i],
                                          i, params->mem);
 
-            this->thread[i]->setStatus(ExecContext::Suspended);
+            this->thread[i]->setStatus(ThreadContext::Suspended);
             //usedTids[i] = true;
             //threadMap[i] = i;
         } else {
-            //Allocate Empty execution context so M5 can use later
+            //Allocate Empty thread so M5 can use later
             //when scheduling threads to CPU
             Process* dummy_proc = NULL;
 
@@ -89,35 +89,35 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
         }
 #endif // !FULL_SYSTEM
 
-        ExecContext *xc_proxy;
+        ThreadContext *tc;
 
-        // Setup the XC that will serve as the interface to the threads/CPU.
-        AlphaXC *alpha_xc = new AlphaXC;
+        // Setup the TC that will serve as the interface to the threads/CPU.
+        AlphaTC *alpha_tc = new AlphaTC;
 
-        // If we're using a checker, then the XC should be the
-        // CheckerExecContext.
+        // If we're using a checker, then the TC should be the
+        // CheckerThreadContext.
         if (params->checker) {
-            xc_proxy = new CheckerExecContext<AlphaXC>(
-                alpha_xc, this->checker);
+            tc = new CheckerThreadContext<AlphaTC>(
+                alpha_tc, this->checker);
         } else {
-            xc_proxy = alpha_xc;
+            tc = alpha_tc;
         }
 
-        alpha_xc->cpu = this;
-        alpha_xc->thread = this->thread[i];
+        alpha_tc->cpu = this;
+        alpha_tc->thread = this->thread[i];
 
 #if FULL_SYSTEM
         // Setup quiesce event.
         this->thread[i]->quiesceEvent =
-            new EndQuiesceEvent(xc_proxy);
+            new EndQuiesceEvent(tc);
         this->thread[i]->lastActivate = 0;
         this->thread[i]->lastSuspend = 0;
 #endif
-        // Give the thread the XC.
-        this->thread[i]->xcProxy = xc_proxy;
+        // Give the thread the TC.
+        this->thread[i]->tc = tc;
 
-        // Add the XC to the CPU's list of XC's.
-        this->execContexts.push_back(xc_proxy);
+        // Add the TC to the CPU's list of TC's.
+        this->threadContexts.push_back(tc);
     }
 
 
@@ -156,7 +156,7 @@ AlphaFullCPU<Impl>::regStats()
 #if FULL_SYSTEM
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::dumpFuncProfile()
+AlphaFullCPU<Impl>::AlphaTC::dumpFuncProfile()
 {
     // Currently not supported
 }
@@ -164,7 +164,7 @@ AlphaFullCPU<Impl>::AlphaXC::dumpFuncProfile()
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
+AlphaFullCPU<Impl>::AlphaTC::takeOverFrom(ThreadContext *old_context)
 {
     // some things should already be set up
     assert(getMemPort() == old_context->getMemPort());
@@ -184,12 +184,12 @@ AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
 #else
     EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
     if (other_quiesce) {
-        // Point the quiesce event's XC at this XC so that it wakes up
+        // Point the quiesce event's TC at this TC so that it wakes up
         // the proper CPU.
-        other_quiesce->xc = this;
+        other_quiesce->tc = this;
     }
     if (thread->quiesceEvent) {
-        thread->quiesceEvent->xc = this;
+        thread->quiesceEvent->tc = this;
     }
 
     // Transfer kernel stats from one CPU to the other.
@@ -198,7 +198,7 @@ AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
     cpu->lockFlag = false;
 #endif
 
-    old_context->setStatus(ExecContext::Unallocated);
+    old_context->setStatus(ThreadContext::Unallocated);
 
     thread->inSyscall = false;
     thread->trapPending = false;
@@ -206,23 +206,23 @@ AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::activate(int delay)
+AlphaFullCPU<Impl>::AlphaTC::activate(int delay)
 {
-    DPRINTF(FullCPU, "Calling activate on AlphaXC\n");
+    DPRINTF(FullCPU, "Calling activate on AlphaTC\n");
 
-    if (thread->status() == ExecContext::Active)
+    if (thread->status() == ThreadContext::Active)
         return;
 
 #if FULL_SYSTEM
     thread->lastActivate = curTick;
 #endif
 
-    if (thread->status() == ExecContext::Unallocated) {
+    if (thread->status() == ThreadContext::Unallocated) {
         cpu->activateWhenReady(thread->tid);
         return;
     }
 
-    thread->setStatus(ExecContext::Active);
+    thread->setStatus(ThreadContext::Active);
 
     // status() == Suspended
     cpu->activateContext(thread->tid, delay);
@@ -230,11 +230,11 @@ AlphaFullCPU<Impl>::AlphaXC::activate(int delay)
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::suspend()
+AlphaFullCPU<Impl>::AlphaTC::suspend()
 {
-    DPRINTF(FullCPU, "Calling suspend on AlphaXC\n");
+    DPRINTF(FullCPU, "Calling suspend on AlphaTC\n");
 
-    if (thread->status() == ExecContext::Suspended)
+    if (thread->status() == ThreadContext::Suspended)
         return;
 
 #if FULL_SYSTEM
@@ -245,44 +245,44 @@ AlphaFullCPU<Impl>::AlphaXC::suspend()
 #if FULL_SYSTEM
     // Don't change the status from active if there are pending interrupts
     if (cpu->check_interrupts()) {
-        assert(status() == ExecContext::Active);
+        assert(status() == ThreadContext::Active);
         return;
     }
 #endif
 */
-    thread->setStatus(ExecContext::Suspended);
+    thread->setStatus(ThreadContext::Suspended);
     cpu->suspendContext(thread->tid);
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::deallocate()
+AlphaFullCPU<Impl>::AlphaTC::deallocate()
 {
-    DPRINTF(FullCPU, "Calling deallocate on AlphaXC\n");
+    DPRINTF(FullCPU, "Calling deallocate on AlphaTC\n");
 
-    if (thread->status() == ExecContext::Unallocated)
+    if (thread->status() == ThreadContext::Unallocated)
         return;
 
-    thread->setStatus(ExecContext::Unallocated);
+    thread->setStatus(ThreadContext::Unallocated);
     cpu->deallocateContext(thread->tid);
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::halt()
+AlphaFullCPU<Impl>::AlphaTC::halt()
 {
-    DPRINTF(FullCPU, "Calling halt on AlphaXC\n");
+    DPRINTF(FullCPU, "Calling halt on AlphaTC\n");
 
-    if (thread->status() == ExecContext::Halted)
+    if (thread->status() == ThreadContext::Halted)
         return;
 
-    thread->setStatus(ExecContext::Halted);
+    thread->setStatus(ThreadContext::Halted);
     cpu->haltContext(thread->tid);
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::regStats(const std::string &name)
+AlphaFullCPU<Impl>::AlphaTC::regStats(const std::string &name)
 {
 #if FULL_SYSTEM
     thread->kernelStats = new Kernel::Statistics(cpu->system);
@@ -292,7 +292,7 @@ AlphaFullCPU<Impl>::AlphaXC::regStats(const std::string &name)
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::serialize(std::ostream &os)
+AlphaFullCPU<Impl>::AlphaTC::serialize(std::ostream &os)
 {
 #if FULL_SYSTEM
     if (thread->kernelStats)
@@ -303,7 +303,7 @@ AlphaFullCPU<Impl>::AlphaXC::serialize(std::ostream &os)
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::unserialize(Checkpoint *cp, const std::string &section)
+AlphaFullCPU<Impl>::AlphaTC::unserialize(Checkpoint *cp, const std::string &section)
 {
 #if FULL_SYSTEM
     if (thread->kernelStats)
@@ -315,46 +315,46 @@ AlphaFullCPU<Impl>::AlphaXC::unserialize(Checkpoint *cp, const std::string &sect
 #if FULL_SYSTEM
 template <class Impl>
 EndQuiesceEvent *
-AlphaFullCPU<Impl>::AlphaXC::getQuiesceEvent()
+AlphaFullCPU<Impl>::AlphaTC::getQuiesceEvent()
 {
     return thread->quiesceEvent;
 }
 
 template <class Impl>
 Tick
-AlphaFullCPU<Impl>::AlphaXC::readLastActivate()
+AlphaFullCPU<Impl>::AlphaTC::readLastActivate()
 {
     return thread->lastActivate;
 }
 
 template <class Impl>
 Tick
-AlphaFullCPU<Impl>::AlphaXC::readLastSuspend()
+AlphaFullCPU<Impl>::AlphaTC::readLastSuspend()
 {
     return thread->lastSuspend;
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::profileClear()
+AlphaFullCPU<Impl>::AlphaTC::profileClear()
 {}
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::profileSample()
+AlphaFullCPU<Impl>::AlphaTC::profileSample()
 {}
 #endif
 
 template <class Impl>
 TheISA::MachInst
-AlphaFullCPU<Impl>::AlphaXC:: getInst()
+AlphaFullCPU<Impl>::AlphaTC:: getInst()
 {
     return thread->inst;
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::copyArchRegs(ExecContext *xc)
+AlphaFullCPU<Impl>::AlphaTC::copyArchRegs(ThreadContext *tc)
 {
     // This function will mess things up unless the ROB is empty and
     // there are no instructions in the pipeline.
@@ -368,44 +368,44 @@ AlphaFullCPU<Impl>::AlphaXC::copyArchRegs(ExecContext *xc)
         DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
                 "now has data %lli.\n",
                 renamed_reg, cpu->readIntReg(renamed_reg),
-                xc->readIntReg(i));
+                tc->readIntReg(i));
 
-        cpu->setIntReg(renamed_reg, xc->readIntReg(i));
+        cpu->setIntReg(renamed_reg, tc->readIntReg(i));
     }
 
     // Then loop through the floating point registers.
     for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) {
         renamed_reg = cpu->renameMap[tid].lookup(i + AlphaISA::FP_Base_DepTag);
         cpu->setFloatRegBits(renamed_reg,
-                             xc->readFloatRegBits(i));
+                             tc->readFloatRegBits(i));
     }
 
     // Copy the misc regs.
-    copyMiscRegs(xc, this);
+    copyMiscRegs(tc, this);
 
     // Then finally set the PC and the next PC.
-    cpu->setPC(xc->readPC(), tid);
-    cpu->setNextPC(xc->readNextPC(), tid);
+    cpu->setPC(tc->readPC(), tid);
+    cpu->setNextPC(tc->readNextPC(), tid);
 #if !FULL_SYSTEM
-    this->thread->funcExeInst = xc->readFuncExeInst();
+    this->thread->funcExeInst = tc->readFuncExeInst();
 #endif
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::clearArchRegs()
+AlphaFullCPU<Impl>::AlphaTC::clearArchRegs()
 {}
 
 template <class Impl>
 uint64_t
-AlphaFullCPU<Impl>::AlphaXC::readIntReg(int reg_idx)
+AlphaFullCPU<Impl>::AlphaTC::readIntReg(int reg_idx)
 {
     return cpu->readArchIntReg(reg_idx, thread->tid);
 }
 
 template <class Impl>
 FloatReg
-AlphaFullCPU<Impl>::AlphaXC::readFloatReg(int reg_idx, int width)
+AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx, int width)
 {
     switch(width) {
       case 32:
@@ -420,41 +420,41 @@ AlphaFullCPU<Impl>::AlphaXC::readFloatReg(int reg_idx, int width)
 
 template <class Impl>
 FloatReg
-AlphaFullCPU<Impl>::AlphaXC::readFloatReg(int reg_idx)
+AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx)
 {
     return cpu->readArchFloatRegSingle(reg_idx, thread->tid);
 }
 
 template <class Impl>
 FloatRegBits
-AlphaFullCPU<Impl>::AlphaXC::readFloatRegBits(int reg_idx, int width)
+AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx, int width)
 {
-    DPRINTF(Fault, "Reading floatint register through the XC!\n");
+    DPRINTF(Fault, "Reading floatint register through the TC!\n");
     return cpu->readArchFloatRegInt(reg_idx, thread->tid);
 }
 
 template <class Impl>
 FloatRegBits
-AlphaFullCPU<Impl>::AlphaXC::readFloatRegBits(int reg_idx)
+AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx)
 {
     return cpu->readArchFloatRegInt(reg_idx, thread->tid);
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setIntReg(int reg_idx, uint64_t val)
+AlphaFullCPU<Impl>::AlphaTC::setIntReg(int reg_idx, uint64_t val)
 {
     cpu->setArchIntReg(reg_idx, val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setFloatReg(int reg_idx, FloatReg val, int width)
+AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width)
 {
     switch(width) {
       case 32:
@@ -467,80 +467,80 @@ AlphaFullCPU<Impl>::AlphaXC::setFloatReg(int reg_idx, FloatReg val, int width)
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setFloatReg(int reg_idx, FloatReg val)
+AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val)
 {
     cpu->setArchFloatRegSingle(reg_idx, val, thread->tid);
 
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setFloatRegBits(int reg_idx, FloatRegBits val,
+AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val,
                                              int width)
 {
-    DPRINTF(Fault, "Setting floatint register through the XC!\n");
+    DPRINTF(Fault, "Setting floatint register through the TC!\n");
     cpu->setArchFloatRegInt(reg_idx, val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setFloatRegBits(int reg_idx, FloatRegBits val)
+AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
     cpu->setArchFloatRegInt(reg_idx, val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setPC(uint64_t val)
+AlphaFullCPU<Impl>::AlphaTC::setPC(uint64_t val)
 {
     cpu->setPC(val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setNextPC(uint64_t val)
+AlphaFullCPU<Impl>::AlphaTC::setNextPC(uint64_t val)
 {
     cpu->setNextPC(val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 Fault
-AlphaFullCPU<Impl>::AlphaXC::setMiscReg(int misc_reg, const MiscReg &val)
+AlphaFullCPU<Impl>::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val)
 {
     Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 
     return ret_fault;
@@ -548,14 +548,14 @@ AlphaFullCPU<Impl>::AlphaXC::setMiscReg(int misc_reg, const MiscReg &val)
 
 template <class Impl>
 Fault
-AlphaFullCPU<Impl>::AlphaXC::setMiscRegWithEffect(int misc_reg,
+AlphaFullCPU<Impl>::AlphaTC::setMiscRegWithEffect(int misc_reg,
                                                   const MiscReg &val)
 {
     Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 
     return ret_fault;
@@ -565,21 +565,21 @@ AlphaFullCPU<Impl>::AlphaXC::setMiscRegWithEffect(int misc_reg,
 
 template <class Impl>
 TheISA::IntReg
-AlphaFullCPU<Impl>::AlphaXC::getSyscallArg(int i)
+AlphaFullCPU<Impl>::AlphaTC::getSyscallArg(int i)
 {
     return cpu->getSyscallArg(i, thread->tid);
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setSyscallArg(int i, IntReg val)
+AlphaFullCPU<Impl>::AlphaTC::setSyscallArg(int i, IntReg val)
 {
     cpu->setSyscallArg(i, val, thread->tid);
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setSyscallReturn(SyscallReturn return_value)
+AlphaFullCPU<Impl>::AlphaTC::setSyscallReturn(SyscallReturn return_value)
 {
     cpu->setSyscallReturn(return_value, thread->tid);
 }
@@ -618,10 +618,10 @@ AlphaFullCPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::squashFromXC(unsigned tid)
+AlphaFullCPU<Impl>::squashFromTC(unsigned tid)
 {
     this->thread[tid]->inSyscall = true;
-    this->commit.generateXCEvent(tid);
+    this->commit.generateTCEvent(tid);
 }
 
 #if FULL_SYSTEM
@@ -632,9 +632,9 @@ AlphaFullCPU<Impl>::post_interrupt(int int_num, int index)
 {
     BaseCPU::post_interrupt(int_num, index);
 
-    if (this->thread[0]->status() == ExecContext::Suspended) {
+    if (this->thread[0]->status() == ThreadContext::Suspended) {
         DPRINTF(IPI,"Suspended Processor awoke\n");
-        this->execContexts[0]->activate();
+        this->threadContexts[0]->activate();
     }
 }
 
@@ -673,7 +673,7 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc, unsigned tid)
 {
     if (this->thread[tid]->kernelStats)
         this->thread[tid]->kernelStats->callpal(palFunc,
-                                                this->execContexts[tid]);
+                                                this->threadContexts[tid]);
 
     switch (palFunc) {
       case PAL::halt:
@@ -696,8 +696,8 @@ template <class Impl>
 void
 AlphaFullCPU<Impl>::trap(Fault fault, unsigned tid)
 {
-    // Pass the thread's XC into the invoke method.
-    fault->invoke(this->execContexts[tid]);
+    // Pass the thread's TC into the invoke method.
+    fault->invoke(this->threadContexts[tid]);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/alpha_dyn_inst_impl.hh b/src/cpu/o3/alpha_dyn_inst_impl.hh
index 3a0727b45..a73cf4a7d 100644
--- a/src/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha_dyn_inst_impl.hh
@@ -67,9 +67,9 @@ Fault
 AlphaDynInst<Impl>::execute()
 {
     // @todo: Pretty convoluted way to avoid squashing from happening
-    // when using the XC during an instruction's execution
+    // when using the TC during an instruction's execution
     // (specifically for instructions that have side-effects that use
-    // the XC).  Fix this.
+    // the TC).  Fix this.
     bool in_syscall = this->thread->inSyscall;
     this->thread->inSyscall = true;
 
@@ -85,9 +85,9 @@ Fault
 AlphaDynInst<Impl>::initiateAcc()
 {
     // @todo: Pretty convoluted way to avoid squashing from happening
-    // when using the XC during an instruction's execution
+    // when using the TC during an instruction's execution
     // (specifically for instructions that have side-effects that use
-    // the XC).  Fix this.
+    // the TC).  Fix this.
     bool in_syscall = this->thread->inSyscall;
     this->thread->inSyscall = true;
 
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index eef96b5fd..b7404c488 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -210,9 +210,9 @@ class DefaultCommit
     void generateTrapEvent(unsigned tid);
 
     /** Records that commit needs to initiate a squash due to an
-     * external state update through the XC.
+     * external state update through the TC.
      */
-    void generateXCEvent(unsigned tid);
+    void generateTCEvent(unsigned tid);
 
   private:
     /** Updates the overall status of commit with the nextStatus, and
@@ -242,8 +242,8 @@ class DefaultCommit
     /** Handles squashing due to a trap. */
     void squashFromTrap(unsigned tid);
 
-    /** Handles squashing due to an XC write. */
-    void squashFromXC(unsigned tid);
+    /** Handles squashing due to an TC write. */
+    void squashFromTC(unsigned tid);
 
     /** Commits as many instructions as possible. */
     void commitInsts();
@@ -344,7 +344,7 @@ class DefaultCommit
     bool trapSquash[Impl::MaxThreads];
 
     /** Records if a thread has to squash this cycle due to an XC write. */
-    bool xcSquash[Impl::MaxThreads];
+    bool tcSquash[Impl::MaxThreads];
 
     /** Priority List used for Commit Policy */
     std::list<unsigned> priority_list;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 629acb310..8ee47e907 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -115,7 +115,7 @@ DefaultCommit<Impl>::DefaultCommit(Params *params)
         commitStatus[i] = Idle;
         changedROBNumEntries[i] = false;
         trapSquash[i] = false;
-        xcSquash[i] = false;
+        tcSquash[i] = false;
         PC[i] = nextPC[i] = 0;
     }
 
@@ -384,7 +384,7 @@ DefaultCommit<Impl>::takeOverFrom()
         commitStatus[i] = Idle;
         changedROBNumEntries[i] = false;
         trapSquash[i] = false;
-        xcSquash[i] = false;
+        tcSquash[i] = false;
     }
     squashCounter = 0;
     rob->takeOverFrom();
@@ -482,11 +482,11 @@ DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
 
 template <class Impl>
 void
-DefaultCommit<Impl>::generateXCEvent(unsigned tid)
+DefaultCommit<Impl>::generateTCEvent(unsigned tid)
 {
-    DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid);
+    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
 
-    xcSquash[tid] = true;
+    tcSquash[tid] = true;
 }
 
 template <class Impl>
@@ -545,11 +545,11 @@ DefaultCommit<Impl>::squashFromTrap(unsigned tid)
 
 template <class Impl>
 void
-DefaultCommit<Impl>::squashFromXC(unsigned tid)
+DefaultCommit<Impl>::squashFromTC(unsigned tid)
 {
     squashAll(tid);
 
-    DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]);
+    DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
 
     thread[tid]->inSyscall = false;
     assert(!thread[tid]->trapPending);
@@ -557,7 +557,7 @@ DefaultCommit<Impl>::squashFromXC(unsigned tid)
     commitStatus[tid] = ROBSquashing;
     cpu->activityThisCycle();
 
-    xcSquash[tid] = false;
+    tcSquash[tid] = false;
 
     ++squashCounter;
 }
@@ -651,7 +651,7 @@ DefaultCommit<Impl>::commit()
         cpu->check_interrupts() &&
         !cpu->inPalMode(readPC()) &&
         !trapSquash[0] &&
-        !xcSquash[0]) {
+        !tcSquash[0]) {
         // Tell fetch that there is an interrupt pending.  This will
         // make fetch wait until it sees a non PAL-mode PC, at which
         // point it stops fetching instructions.
@@ -720,10 +720,10 @@ DefaultCommit<Impl>::commit()
         // Not sure which one takes priority.  I think if we have
         // both, that's a bad sign.
         if (trapSquash[tid] == true) {
-            assert(!xcSquash[tid]);
+            assert(!tcSquash[tid]);
             squashFromTrap(tid);
-        } else if (xcSquash[tid] == true) {
-            squashFromXC(tid);
+        } else if (tcSquash[tid] == true) {
+            squashFromTC(tid);
         }
 
         // Squashed sequence number must be older than youngest valid
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index ec804ee96..f523766cc 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -39,7 +39,7 @@
 #include "cpu/activity.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/o3/alpha_dyn_inst.hh"
 #include "cpu/o3/alpha_impl.hh"
 #include "cpu/o3/cpu.hh"
@@ -384,7 +384,7 @@ void
 FullO3CPU<Impl>::init()
 {
     if (!deferRegistration) {
-        registerExecContexts();
+        registerThreadContexts();
     }
 
     // Set inSyscall so that the CPU doesn't squash when initially
@@ -394,17 +394,17 @@ FullO3CPU<Impl>::init()
 
     for (int tid=0; tid < number_of_threads; tid++) {
 #if FULL_SYSTEM
-        ExecContext *src_xc = execContexts[tid];
+        ThreadContext *src_tc = threadContexts[tid];
 #else
-        ExecContext *src_xc = thread[tid]->getXCProxy();
+        ThreadContext *src_tc = thread[tid]->getTC();
 #endif
         // Threads start in the Suspended State
-        if (src_xc->status() != ExecContext::Suspended) {
+        if (src_tc->status() != ThreadContext::Suspended) {
             continue;
         }
 
 #if FULL_SYSTEM
-        TheISA::initCPU(src_xc, src_xc->readCpuId());
+        TheISA::initCPU(src_tc, src_tc->readCpuId());
 #endif
     }
 
@@ -430,9 +430,9 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
     // and not in the CPUExecContext.
 #if 0
 #if FULL_SYSTEM
-    ExecContext *src_xc = system->execContexts[tid];
+    ThreadContext *src_tc = system->threadContexts[tid];
 #else
-    CPUExecContext *src_xc = thread[tid];
+    CPUExecContext *src_tc = thread[tid];
 #endif
 
     //Bind Int Regs to Rename Map
@@ -452,13 +452,13 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
     }
 
     //Copy Thread Data Into RegFile
-    this->copyFromXC(tid);
+    this->copyFromTC(tid);
 
     //Set PC/NPC
-    regFile.pc[tid]  = src_xc->readPC();
-    regFile.npc[tid] = src_xc->readNextPC();
+    regFile.pc[tid]  = src_tc->readPC();
+    regFile.npc[tid] = src_tc->readNextPC();
 
-    src_xc->setStatus(ExecContext::Active);
+    src_tc->setStatus(ThreadContext::Active);
 
     activateContext(tid,1);
 
@@ -496,7 +496,7 @@ FullO3CPU<Impl>::removeThread(unsigned tid)
      * in the sense that it's finished (exiting)? If the thread is just
      * being suspended we might...
      */
-//    this->copyToXC(tid);
+//    this->copyToTC(tid);
 
     //Squash Throughout Pipeline
     fetch.squash(0,tid);
@@ -745,9 +745,9 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
 
     // Set all statuses to active, schedule the CPU's tick event.
     // @todo: Fix up statuses so this is handled properly
-    for (int i = 0; i < execContexts.size(); ++i) {
-        ExecContext *xc = execContexts[i];
-        if (xc->status() == ExecContext::Active && _status != Running) {
+    for (int i = 0; i < threadContexts.size(); ++i) {
+        ThreadContext *tc = threadContexts[i];
+        if (tc->status() == ThreadContext::Active && _status != Running) {
             _status = Running;
             tickEvent.schedule(curTick);
         }
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index c2c5289bf..69f52f147 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -52,7 +52,7 @@
 
 template <class>
 class Checker;
-class ExecContext;
+class ThreadContext;
 class MemObject;
 class Process;
 
@@ -455,10 +455,10 @@ class FullO3CPU : public BaseFullCPU
     int getFreeTid();
 
   public:
-    /** Returns a pointer to a thread's exec context. */
-    ExecContext *xcBase(unsigned tid)
+    /** Returns a pointer to a thread context. */
+    ThreadContext *tcBase(unsigned tid)
     {
-        return thread[tid]->getXCProxy();
+        return thread[tid]->getTC();
     }
 
     /** The global sequence number counter. */
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 3a41de721..f3793db6d 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1011,7 +1011,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                     tid, instruction->staticInst->disassemble(fetch_PC));
 
             instruction->traceData =
-                Trace::getInstRecord(curTick, cpu->xcBase(tid), cpu,
+                Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
                                      instruction->staticInst,
                                      instruction->readPC(),tid);
 
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index c2ad75060..ee95b9ab8 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -240,7 +240,7 @@ class PhysRegFile
                                   unsigned thread_id)
     {
         return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
-                                                     cpu->xcBase(thread_id));
+                                                     cpu->tcBase(thread_id));
     }
 
     Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
@@ -252,7 +252,7 @@ class PhysRegFile
                                unsigned thread_id)
     {
         return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
-                                                    cpu->xcBase(thread_id));
+                                                    cpu->tcBase(thread_id));
     }
 
 #if FULL_SYSTEM
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 3fa60f093..7322161e6 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -31,7 +31,7 @@
 
 #include "arch/faults.hh"
 #include "arch/isa_traits.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
 
 class Event;
@@ -49,13 +49,13 @@ class Process;
 /**
  * Class that has various thread state, such as the status, the
  * current instruction being processed, whether or not the thread has
- * a trap pending or is being externally updated, the ExecContext
- * proxy pointer, etc.  It also handles anything related to a specific
+ * a trap pending or is being externally updated, the ThreadContext
+ * pointer, etc.  It also handles anything related to a specific
  * thread's process, such as syscalls and checking valid addresses.
  */
 template <class Impl>
 struct O3ThreadState : public ThreadState {
-    typedef ExecContext::Status Status;
+    typedef ThreadContext::Status Status;
     typedef typename Impl::FullCPU FullCPU;
 
     /** Current status of the thread. */
@@ -93,12 +93,11 @@ struct O3ThreadState : public ThreadState {
     { }
 #endif
 
-    /** Pointer to the ExecContext of this thread.  @todo: Don't call
-     this a proxy.*/
-    ExecContext *xcProxy;
+    /** Pointer to the ThreadContext of this thread. */
+    ThreadContext *tc;
 
-    /** Returns a pointer to the XC of this thread. */
-    ExecContext *getXCProxy() { return xcProxy; }
+    /** Returns a pointer to the TC of this thread. */
+    ThreadContext *getTC() { return tc; }
 
     /** Returns the status of this thread. */
     Status status() const { return _status; }
@@ -121,7 +120,7 @@ struct O3ThreadState : public ThreadState {
 
 #if !FULL_SYSTEM
     /** Handles the syscall. */
-    void syscall(int64_t callnum) { process->syscall(callnum, xcProxy); }
+    void syscall(int64_t callnum) { process->syscall(callnum, tc); }
 #endif
 };