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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:49 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:49 -0600 |
| commit | 7391ea6de63578722d97c9169e60db5b06754137 (patch) | |
| tree | c544188de95cc72b74467bdec048883f300a5b61 /src/cpu/o3 | |
| parent | ae3d45685512b75f878eb9d7917680fc3971988e (diff) | |
| download | gem5-7391ea6de63578722d97c9169e60db5b06754137.tar.xz | |
ARM: Do something for ISB, DSB, DMB
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/commit_impl.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 01e235722..104e7fb58 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -1177,7 +1177,8 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) } } #endif - + DPRINTF(Commit, "Committing instruction with [sn:%lli]\n", + head_inst->seqNum); if (head_inst->traceData) { head_inst->traceData->setFetchSeq(head_inst->seqNum); head_inst->traceData->setCPSeq(thread[tid]->numInst); |