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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-06-09 23:18:46 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-06-09 23:18:46 -0400 |
| commit | 95019d0c6f1675f42d899f2899e06d3017088f25 (patch) | |
| tree | 7618cd95da8299faff8dd682e088ee707cae6a7f /src/cpu/o3 | |
| parent | 6de5d73a999240f92f050393bb10028968275835 (diff) | |
| parent | 29e34a739b991af8d8e1eafe75ecb0904c324dc8 (diff) | |
| download | gem5-95019d0c6f1675f42d899f2899e06d3017088f25.tar.xz | |
Merge vm1.(none):/home/stever/bk/newmem
into vm1.(none):/home/stever/bk/newmem-py
src/python/m5/__init__.py:
src/sim/syscall_emul.cc:
Hand merge.
--HG--
extra : convert_revision : e2542735323e648383c89382421d98a7d1d761bf
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/alpha_cpu_impl.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha_cpu_impl.hh index fb2fea8e6..98290e57f 100644 --- a/src/cpu/o3/alpha_cpu_impl.hh +++ b/src/cpu/o3/alpha_cpu_impl.hh @@ -735,7 +735,7 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc, unsigned tid) case PAL::halt: halt(); if (--System::numSystemsRunning == 0) - new SimExitEvent("all cpus halted"); + exitSimLoop("all cpus halted"); break; case PAL::bpt: |