diff options
author | Kevin Lim <ktlim@umich.edu> | 2006-11-10 12:44:15 -0500 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-11-10 12:44:15 -0500 |
commit | b5e68fb54677f601bb00c23af52db8fd6571301f (patch) | |
tree | dc3c17198ba4010d907ecd8cb7189aa7959948d4 /src/cpu/o3 | |
parent | 264f9ce374ff4689fec3c32d8289fe76b0b65078 (diff) | |
parent | 9ef51f2dbaba88c10366d708f0ca872bb39064e4 (diff) | |
download | gem5-b5e68fb54677f601bb00c23af52db8fd6571301f.tar.xz |
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
--HG--
extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/alpha/cpu.hh | 23 | ||||
-rw-r--r-- | src/cpu/o3/alpha/cpu_builder.cc | 10 | ||||
-rw-r--r-- | src/cpu/o3/alpha/cpu_impl.hh | 96 | ||||
-rw-r--r-- | src/cpu/o3/alpha/dyn_inst.hh | 15 | ||||
-rw-r--r-- | src/cpu/o3/alpha/dyn_inst_impl.hh | 23 | ||||
-rw-r--r-- | src/cpu/o3/alpha/params.hh | 11 | ||||
-rw-r--r-- | src/cpu/o3/alpha/thread_context.hh | 9 | ||||
-rw-r--r-- | src/cpu/o3/checker_builder.cc | 4 | ||||
-rw-r--r-- | src/cpu/o3/commit_impl.hh | 7 | ||||
-rw-r--r-- | src/cpu/o3/cpu.cc | 2 | ||||
-rw-r--r-- | src/cpu/o3/cpu.hh | 3 | ||||
-rw-r--r-- | src/cpu/o3/fetch.hh | 2 | ||||
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 23 | ||||
-rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 1 | ||||
-rw-r--r-- | src/cpu/o3/mem_dep_unit.hh | 2 | ||||
-rw-r--r-- | src/cpu/o3/mem_dep_unit_impl.hh | 13 | ||||
-rwxr-xr-x | src/cpu/o3/mips/cpu.hh | 7 | ||||
-rw-r--r-- | src/cpu/o3/mips/cpu_builder.cc | 6 | ||||
-rw-r--r-- | src/cpu/o3/mips/cpu_impl.hh | 31 | ||||
-rwxr-xr-x | src/cpu/o3/mips/dyn_inst.hh | 11 | ||||
-rwxr-xr-x | src/cpu/o3/params.hh | 2 | ||||
-rw-r--r-- | src/cpu/o3/regfile.hh | 23 | ||||
-rwxr-xr-x | src/cpu/o3/thread_context.hh | 10 | ||||
-rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 15 | ||||
-rw-r--r-- | src/cpu/o3/thread_state.hh | 7 |
25 files changed, 106 insertions, 250 deletions
diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index 9d97f9701..b62550062 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -37,6 +37,12 @@ #include "cpu/o3/cpu.hh" #include "sim/byteswap.hh" +namespace TheISA +{ + class ITB; + class DTB; +} + class EndQuiesceEvent; namespace Kernel { class Statistics; @@ -73,9 +79,9 @@ class AlphaO3CPU : public FullO3CPU<Impl> #if FULL_SYSTEM /** ITB pointer. */ - AlphaITB *itb; + AlphaISA::ITB *itb; /** DTB pointer. */ - AlphaDTB *dtb; + AlphaISA::DTB *dtb; #endif /** Registers statistics. */ @@ -126,15 +132,15 @@ class AlphaO3CPU : public FullO3CPU<Impl> /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid); + MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid); /** Sets a miscellaneous register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid); + void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid); + void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid); /** Initiates a squash of all in-flight instructions for a given * thread. The source of the squash is an external update of @@ -145,15 +151,8 @@ class AlphaO3CPU : public FullO3CPU<Impl> #if FULL_SYSTEM /** Posts an interrupt. */ void post_interrupt(int int_num, int index); - /** Reads the interrupt flag. */ - int readIntrFlag(); - /** Sets the interrupt flags. */ - void setIntrFlag(int val); /** HW return from error interrupt. */ Fault hwrei(unsigned tid); - /** Returns if a specific PC is a PAL mode PC. */ - bool inPalMode(uint64_t PC) - { return AlphaISA::PcPAL(PC); } bool simPalCheck(int palFunc, unsigned tid); diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc index ff123a6f7..be8ad8de6 100644 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ b/src/cpu/o3/alpha/cpu_builder.cc @@ -54,15 +54,13 @@ Param<int> activity; #if FULL_SYSTEM SimObjectParam<System *> system; Param<int> cpu_id; -SimObjectParam<AlphaITB *> itb; -SimObjectParam<AlphaDTB *> dtb; +SimObjectParam<AlphaISA::ITB *> itb; +SimObjectParam<AlphaISA::DTB *> dtb; Param<Tick> profile; #else SimObjectVectorParam<Process *> workload; #endif // FULL_SYSTEM -SimObjectParam<MemObject *> mem; - SimObjectParam<BaseCPU *> checker; Param<Counter> max_insts_any_thread; @@ -169,8 +167,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) INIT_PARAM(workload, "Processes to run"), #endif // FULL_SYSTEM - INIT_PARAM(mem, "Memory"), - INIT_PARAM_DFLT(checker, "Checker CPU", NULL), INIT_PARAM_DFLT(max_insts_any_thread, @@ -314,8 +310,6 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->workload = workload; #endif // FULL_SYSTEM - params->mem = mem; - params->checker = checker; params->max_insts_any_thread = max_insts_any_thread; diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 8c3d7ee32..618716fc6 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -48,8 +48,8 @@ #if FULL_SYSTEM #include "arch/alpha/osfpal.hh" #include "arch/isa_traits.hh" +#include "arch/kernel_stats.hh" #include "cpu/quiesce_event.hh" -#include "kern/kernel_stats.hh" #include "sim/sim_exit.hh" #include "sim/system.hh" #endif @@ -77,24 +77,10 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) if (i < params->workload.size()) { DPRINTF(O3CPU, "Workload[%i] process is %#x", i, this->thread[i]); - this->thread[i] = new Thread(this, i, params->workload[i], - i, params->mem); + this->thread[i] = new Thread(this, i, params->workload[i], i); this->thread[i]->setStatus(ThreadContext::Suspended); -#if !FULL_SYSTEM - /* Use this port to for syscall emulation writes to memory. */ - Port *mem_port; - TranslatingPort *trans_port; - trans_port = new TranslatingPort(csprintf("%s-%d-funcport", - name(), i), - params->workload[i]->pTable, - false); - mem_port = params->mem->getPort("functional"); - mem_port->setPeer(trans_port); - trans_port->setPeer(mem_port); - this->thread[i]->setMemPort(trans_port); -#endif //usedTids[i] = true; //threadMap[i] = i; } else { @@ -102,7 +88,7 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) //when scheduling threads to CPU Process* dummy_proc = NULL; - this->thread[i] = new Thread(this, i, dummy_proc, i, params->mem); + this->thread[i] = new Thread(this, i, dummy_proc, i); //usedTids[i] = false; } #endif // !FULL_SYSTEM @@ -198,25 +184,24 @@ AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) template <class Impl> TheISA::MiscReg -AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault, - unsigned tid) +AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid) { - return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid); + return this->regFile.readMiscRegWithEffect(misc_reg, tid); } template <class Impl> -Fault +void AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) { - return this->regFile.setMiscReg(misc_reg, val, tid); + this->regFile.setMiscReg(misc_reg, val, tid); } template <class Impl> -Fault +void AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid) { - return this->regFile.setMiscRegWithEffect(misc_reg, val, tid); + this->regFile.setMiscRegWithEffect(misc_reg, val, tid); } template <class Impl> @@ -242,20 +227,6 @@ AlphaO3CPU<Impl>::post_interrupt(int int_num, int index) } template <class Impl> -int -AlphaO3CPU<Impl>::readIntrFlag() -{ - return this->regFile.readIntrFlag(); -} - -template <class Impl> -void -AlphaO3CPU<Impl>::setIntrFlag(int val) -{ - this->regFile.setIntrFlag(val); -} - -template <class Impl> Fault AlphaO3CPU<Impl>::hwrei(unsigned tid) { @@ -299,7 +270,6 @@ template <class Impl> void AlphaO3CPU<Impl>::processInterrupts() { - using namespace TheISA; // Check for interrupts here. For now can copy the code that // exists within isa_fullsys_traits.hh. Also assume that thread 0 // is the one that handles the interrupts. @@ -308,51 +278,11 @@ AlphaO3CPU<Impl>::processInterrupts() // Check if there are any outstanding interrupts //Handle the interrupts - int ipl = 0; - int summary = 0; - - this->checkInterrupts = false; - - if (this->readMiscReg(IPR_ASTRR, 0)) - panic("asynchronous traps not implemented\n"); - - if (this->readMiscReg(IPR_SIRR, 0)) { - for (int i = INTLEVEL_SOFTWARE_MIN; - i < INTLEVEL_SOFTWARE_MAX; i++) { - if (this->readMiscReg(IPR_SIRR, 0) & (ULL(1) << i)) { - // See table 4-19 of the 21164 hardware reference - ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; - summary |= (ULL(1) << i); - } - } - } - - uint64_t interrupts = this->intr_status(); + Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0)); - if (interrupts) { - for (int i = INTLEVEL_EXTERNAL_MIN; - i < INTLEVEL_EXTERNAL_MAX; i++) { - if (interrupts & (ULL(1) << i)) { - // See table 4-19 of the 21164 hardware reference - ipl = i; - summary |= (ULL(1) << i); - } - } - } - - if (ipl && ipl > this->readMiscReg(IPR_IPLR, 0)) { - this->setMiscReg(IPR_ISR, summary, 0); - this->setMiscReg(IPR_INTID, ipl, 0); - // Checker needs to know these two registers were updated. -#if USE_CHECKER - if (this->checker) { - this->checker->threadBase()->setMiscReg(IPR_ISR, summary); - this->checker->threadBase()->setMiscReg(IPR_INTID, ipl); - } -#endif - this->trap(Fault(new InterruptFault), 0); - DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - this->readMiscReg(IPR_IPLR, 0), ipl, summary); + if (interrupt != NoFault) { + this->checkInterrupts = false; + this->trap(interrupt, 0); } } diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index 294aadde8..31df8ff78 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -102,14 +102,13 @@ class AlphaDynInst : public BaseDynInst<Impl> /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + MiscReg readMiscRegWithEffect(int misc_reg) { - return this->cpu->readMiscRegWithEffect(misc_reg, fault, - this->threadNumber); + return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber); } /** Sets a misc. register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { this->instResult.integer = val; return this->cpu->setMiscReg(misc_reg, val, this->threadNumber); @@ -118,7 +117,7 @@ class AlphaDynInst : public BaseDynInst<Impl> /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { return this->cpu->setMiscRegWithEffect(misc_reg, val, this->threadNumber); @@ -127,12 +126,6 @@ class AlphaDynInst : public BaseDynInst<Impl> #if FULL_SYSTEM /** Calls hardware return from error interrupt. */ Fault hwrei(); - /** Reads interrupt flag. */ - int readIntrFlag(); - /** Sets interrupt flag. */ - void setIntrFlag(int val); - /** Checks if system is in PAL mode. */ - bool inPalMode(); /** Traps to handle specified fault. */ void trap(Fault fault); bool simPalCheck(int palFunc); diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh index b273a7b9b..6fc548a85 100644 --- a/src/cpu/o3/alpha/dyn_inst_impl.hh +++ b/src/cpu/o3/alpha/dyn_inst_impl.hh @@ -113,7 +113,7 @@ Fault AlphaDynInst<Impl>::hwrei() { // Can only do a hwrei when in pal mode. - if (!this->cpu->inPalMode(this->readPC())) + if (!(this->readPC() & 0x3)) return new AlphaISA::UnimplementedOpcodeFault; // Set the next PC based on the value of the EXC_ADDR IPR. @@ -128,27 +128,6 @@ AlphaDynInst<Impl>::hwrei() } template <class Impl> -int -AlphaDynInst<Impl>::readIntrFlag() -{ - return this->cpu->readIntrFlag(); -} - -template <class Impl> -void -AlphaDynInst<Impl>::setIntrFlag(int val) -{ - this->cpu->setIntrFlag(val); -} - -template <class Impl> -bool -AlphaDynInst<Impl>::inPalMode() -{ - return this->cpu->inPalMode(this->PC); -} - -template <class Impl> void AlphaDynInst<Impl>::trap(Fault fault) { diff --git a/src/cpu/o3/alpha/params.hh b/src/cpu/o3/alpha/params.hh index c618cee08..b6b84b2a1 100644 --- a/src/cpu/o3/alpha/params.hh +++ b/src/cpu/o3/alpha/params.hh @@ -35,8 +35,11 @@ #include "cpu/o3/params.hh" //Forward declarations -class AlphaDTB; -class AlphaITB; +namespace AlphaISA +{ + class DTB; + class ITB; +} class MemObject; class Process; class System; @@ -52,8 +55,8 @@ class AlphaSimpleParams : public O3Params public: #if FULL_SYSTEM - AlphaITB *itb; - AlphaDTB *dtb; + AlphaISA::ITB *itb; + AlphaISA::DTB *dtb; #endif }; diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh index 70a09940f..bcecb7087 100644 --- a/src/cpu/o3/alpha/thread_context.hh +++ b/src/cpu/o3/alpha/thread_context.hh @@ -37,21 +37,16 @@ class AlphaTC : public O3ThreadContext<Impl> public: #if FULL_SYSTEM /** Returns a pointer to the ITB. */ - virtual AlphaITB *getITBPtr() { return this->cpu->itb; } + virtual AlphaISA::ITB *getITBPtr() { return this->cpu->itb; } /** Returns a pointer to the DTB. */ - virtual AlphaDTB *getDTBPtr() { return this->cpu->dtb; } + virtual AlphaISA::DTB *getDTBPtr() { return this->cpu->dtb; } /** Returns pointer to the quiesce event. */ virtual EndQuiesceEvent *getQuiesceEvent() { return this->thread->quiesceEvent; } - - /** Returns if the thread is currently in PAL mode, based on - * the PC's value. */ - virtual bool inPalMode() - { return TheISA::PcPAL(this->cpu->readPC(this->thread->readTid())); } #endif virtual uint64_t readNextNPC() diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc index 02c817499..8b028e3a0 100644 --- a/src/cpu/o3/checker_builder.cc +++ b/src/cpu/o3/checker_builder.cc @@ -67,8 +67,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker) Param<Tick> progress_interval; #if FULL_SYSTEM - SimObjectParam<AlphaITB *> itb; - SimObjectParam<AlphaDTB *> dtb; + SimObjectParam<TheISA::ITB *> itb; + SimObjectParam<TheISA::DTB *> dtb; SimObjectParam<System *> system; Param<int> cpu_id; Param<Tick> profile; diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index ecf6ed632..30052a148 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -35,6 +35,7 @@ #include <algorithm> #include <string> +#include "arch/utility.hh" #include "base/loader/symtab.hh" #include "base/timebuf.hh" #include "cpu/exetrace.hh" @@ -638,8 +639,7 @@ DefaultCommit<Impl>::commit() // and no other traps or external squashes are currently pending. // @todo: Allow other threads to handle interrupts. if (cpu->checkInterrupts && - cpu->check_interrupts() && - !cpu->inPalMode(readPC()) && + cpu->check_interrupts(cpu->tcBase(0)) && !trapSquash[0] && !tcSquash[0]) { // Tell fetch that there is an interrupt pending. This will @@ -1085,8 +1085,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) #if FULL_SYSTEM if (thread[tid]->profile) { -// bool usermode = -// (cpu->readMiscReg(AlphaISA::IPR_DTB_CM, tid) & 0x18) != 0; +// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); // thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); thread[tid]->profilePC = head_inst->readPC(); ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 367508288..dfe42d882 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -187,7 +187,6 @@ FullO3CPU<Impl>::FullO3CPU(Params *params) system(params->system), physmem(system->physmem), #endif // FULL_SYSTEM - mem(params->mem), drainCount(0), deferRegistration(params->deferRegistration), numThreads(number_of_threads) @@ -204,7 +203,6 @@ FullO3CPU<Impl>::FullO3CPU(Params *params) #if USE_CHECKER BaseCPU *temp_checker = params->checker; checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); - checker->setMemory(mem); #if FULL_SYSTEM checker->setSystem(params->system); #endif diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index fe510519c..2bf9cb23b 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -620,9 +620,6 @@ class FullO3CPU : public BaseO3CPU PhysicalMemory *physmem; #endif - /** Pointer to memory. */ - MemObject *mem; - /** Event to call process() on once draining has completed. */ Event *drainEvent; diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 5555bff85..cc9a8abf5 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -329,8 +329,6 @@ class DefaultFetch /** Wire used to write any information heading to decode. */ typename TimeBuffer<FetchStruct>::wire toDecode; - MemObject *mem; - /** Icache interface. */ IcachePort *icachePort; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index f1d6cb64f..350ecd52d 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -45,7 +45,6 @@ #if FULL_SYSTEM #include "arch/tlb.hh" #include "arch/vtophys.hh" -#include "base/remote_gdb.hh" #include "sim/system.hh" #endif // FULL_SYSTEM @@ -98,8 +97,7 @@ DefaultFetch<Impl>::IcachePort::recvRetry() template<class Impl> DefaultFetch<Impl>::DefaultFetch(Params *params) - : mem(params->mem), - branchPred(params), + : branchPred(params), decodeToFetchDelay(params->decodeToFetchDelay), renameToFetchDelay(params->renameToFetchDelay), iewToFetchDelay(params->iewToFetchDelay), @@ -562,14 +560,9 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid { Fault fault = NoFault; -#if FULL_SYSTEM - // Flag to say whether or not address is physical addr. - unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0; -#else - unsigned flags = 0; -#endif // FULL_SYSTEM - - if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) { + //AlphaDep + if (cacheBlocked || isSwitchedOut() || + (interruptPending && (fetch_PC & 0x3))) { // Hold off fetch from getting new instructions when: // Cache is blocked, or // while an interrupt is pending and we're not in PAL mode, or @@ -588,7 +581,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid // Setup the memReq to do a read of the first instruction's address. // Set the appropriate read size and flags as well. // Build request here. - RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags, + RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, 0, fetch_PC, cpu->readCpuId(), tid); memReq[tid] = mem_req; @@ -1120,7 +1113,11 @@ DefaultFetch<Impl>::fetch(bool &status_change) inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> (&cacheData[tid][offset])); - ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid)); +#if THE_ISA == ALPHA_ISA + ext_inst = TheISA::makeExtMI(inst, fetch_PC); +#elif THE_ISA == SPARC_ISA + ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); +#endif // Create a new DynInst from the instruction fetched. DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 8a63ff011..4facea9f9 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -132,6 +132,7 @@ LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, usedPorts = 0; cachePorts = params->cachePorts; + retryPkt = NULL; memDepViolator = NULL; blockedLoadSeqNum = 0; diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh index e399f0133..a12a3001b 100644 --- a/src/cpu/o3/mem_dep_unit.hh +++ b/src/cpu/o3/mem_dep_unit.hh @@ -69,7 +69,7 @@ class MemDepUnit { typedef typename Impl::DynInstPtr DynInstPtr; /** Empty constructor. Must call init() prior to using in this case. */ - MemDepUnit() {} + MemDepUnit(); /** Constructs a MemDepUnit with given parameters. */ MemDepUnit(Params *params); diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh index c649ca385..f19980fd5 100644 --- a/src/cpu/o3/mem_dep_unit_impl.hh +++ b/src/cpu/o3/mem_dep_unit_impl.hh @@ -34,6 +34,13 @@ #include "cpu/o3/mem_dep_unit.hh" template <class MemDepPred, class Impl> +MemDepUnit<MemDepPred, Impl>::MemDepUnit() + : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), + storeBarrierSN(0), iqPtr(NULL) +{ +} + +template <class MemDepPred, class Impl> MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params) : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) @@ -160,8 +167,12 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) // producing memrefs/stores. InstSeqNum producing_store; if (inst->isLoad() && loadBarrier) { + DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", + loadBarrierSN); producing_store = loadBarrierSN; } else if (inst->isStore() && storeBarrier) { + DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", + storeBarrierSN); producing_store = storeBarrierSN; } else { producing_store = depPred.checkInst(inst->readPC()); @@ -171,10 +182,12 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) // If there is a producing store, try to find the entry. if (producing_store != 0) { + DPRINTF(MemDepUnit, "Searching for producer\n"); MemDepHashIt hash_it = memDepHash.find(producing_store); if (hash_it != memDepHash.end()) { store_entry = (*hash_it).second; + DPRINTF(MemDepUnit, "Proucer found\n"); } } diff --git a/src/cpu/o3/mips/cpu.hh b/src/cpu/o3/mips/cpu.hh index bf04b9f69..7e6268cdf 100755 --- a/src/cpu/o3/mips/cpu.hh +++ b/src/cpu/o3/mips/cpu.hh @@ -92,16 +92,15 @@ class MipsO3CPU : public FullO3CPU<Impl> /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegWithEffect(int misc_reg, - Fault &fault, unsigned tid); + TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid); /** Sets a miscellaneous register. */ - Fault setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); + void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, + void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Initiates a squash of all in-flight instructions for a given diff --git a/src/cpu/o3/mips/cpu_builder.cc b/src/cpu/o3/mips/cpu_builder.cc index f1c3b33a5..ee9f2b48d 100644 --- a/src/cpu/o3/mips/cpu_builder.cc +++ b/src/cpu/o3/mips/cpu_builder.cc @@ -54,8 +54,6 @@ Param<int> activity; SimObjectVectorParam<Process *> workload; -SimObjectParam<MemObject *> mem; - SimObjectParam<BaseCPU *> checker; Param<Counter> max_insts_any_thread; @@ -153,8 +151,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) INIT_PARAM(workload, "Processes to run"), - INIT_PARAM(mem, "Memory"), - INIT_PARAM_DFLT(checker, "Checker CPU", NULL), INIT_PARAM_DFLT(max_insts_any_thread, @@ -284,8 +280,6 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->workload = workload; - params->mem = mem; - params->checker = checker; params->max_insts_any_thread = max_insts_any_thread; diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh index e08741626..08e9ba483 100644 --- a/src/cpu/o3/mips/cpu_impl.hh +++ b/src/cpu/o3/mips/cpu_impl.hh @@ -58,24 +58,10 @@ MipsO3CPU<Impl>::MipsO3CPU(Params *params) if (i < params->workload.size()) { DPRINTF(O3CPU, "Workload[%i] process is %#x", i, this->thread[i]); - this->thread[i] = new Thread(this, i, params->workload[i], - i, params->mem); + this->thread[i] = new Thread(this, i, params->workload[i], i); this->thread[i]->setStatus(ThreadContext::Suspended); - - /* Use this port to for syscall emulation writes to memory. */ - Port *mem_port; - TranslatingPort *trans_port; - trans_port = new TranslatingPort(csprintf("%s-%d-funcport", - name(), i), - params->workload[i]->pTable, - false); - mem_port = params->mem->getPort("functional"); - mem_port->setPeer(trans_port); - trans_port->setPeer(mem_port); - this->thread[i]->setMemPort(trans_port); - //usedTids[i] = true; //threadMap[i] = i; } else { @@ -83,7 +69,7 @@ MipsO3CPU<Impl>::MipsO3CPU(Params *params) //when scheduling threads to CPU Process* dummy_proc = NULL; - this->thread[i] = new Thread(this, i, dummy_proc, i, params->mem); + this->thread[i] = new Thread(this, i, dummy_proc, i); //usedTids[i] = false; } @@ -156,25 +142,24 @@ MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) template <class Impl> MiscReg -MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault, - unsigned tid) +MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid) { - return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid); + return this->regFile.readMiscRegWithEffect(misc_reg, tid); } template <class Impl> -Fault +void MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) { - return this->regFile.setMiscReg(misc_reg, val, tid); + this->regFile.setMiscReg(misc_reg, val, tid); } template <class Impl> -Fault +void MipsO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid) { - return this->regFile.setMiscRegWithEffect(misc_reg, val, tid); + this->regFile.setMiscRegWithEffect(misc_reg, val, tid); } template <class Impl> diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh index aa30bfa1e..9e95b2bfb 100755 --- a/src/cpu/o3/mips/dyn_inst.hh +++ b/src/cpu/o3/mips/dyn_inst.hh @@ -103,23 +103,22 @@ class MipsDynInst : public BaseDynInst<Impl> /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + MiscReg readMiscRegWithEffect(int misc_reg) { - return this->cpu->readMiscRegWithEffect(misc_reg, fault, - this->threadNumber); + return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber); } /** Sets a misc. register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { this->instResult.integer = val; - return this->cpu->setMiscReg(misc_reg, val, this->threadNumber); + this->cpu->setMiscReg(misc_reg, val, this->threadNumber); } /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { return this->cpu->setMiscRegWithEffect(misc_reg, val, this->threadNumber); diff --git a/src/cpu/o3/params.hh b/src/cpu/o3/params.hh index 1c234bcd7..b487778c6 100755 --- a/src/cpu/o3/params.hh +++ b/src/cpu/o3/params.hh @@ -54,8 +54,6 @@ class O3Params : public BaseO3CPU::Params Process *process; #endif // FULL_SYSTEM - MemObject *mem; - BaseCPU *checker; // diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 512cf0721..598af123e 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -37,11 +37,9 @@ #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/o3/comm.hh" -#include "sim/faults.hh" #if FULL_SYSTEM -#include "kern/kernel_stats.hh" - +#include "arch/kernel_stats.hh" #endif #include <vector> @@ -232,31 +230,24 @@ class PhysRegFile return miscRegs[thread_id].readReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, - unsigned thread_id) + MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id) { - return miscRegs[thread_id].readRegWithEffect(misc_reg, fault, + return miscRegs[thread_id].readRegWithEffect(misc_reg, cpu->tcBase(thread_id)); } - Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) + void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) { - return miscRegs[thread_id].setReg(misc_reg, val); + miscRegs[thread_id].setReg(misc_reg, val); } - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, + void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned thread_id) { - return miscRegs[thread_id].setRegWithEffect(misc_reg, val, + miscRegs[thread_id].setRegWithEffect(misc_reg, val, cpu->tcBase(thread_id)); } -#if FULL_SYSTEM - int readIntrFlag() { return intrflag; } - /** Sets an interrupt flag. */ - void setIntrFlag(int val) { intrflag = val; } -#endif - public: /** (signed) integer register file. */ IntReg *intRegFile; diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 9ca02b9f3..daee2fc7d 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -83,7 +83,7 @@ class O3ThreadContext : public ThreadContext virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } /** Returns a pointer to this thread's kernel statistics. */ - virtual Kernel::Statistics *getKernelStats() + virtual TheISA::Kernel::Statistics *getKernelStats() { return thread->kernelStats; } virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } @@ -201,15 +201,15 @@ class O3ThreadContext : public ThreadContext /** Reads a misc. register, including any side-effects the * read might have as defined by the architecture. */ - virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) - { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->readTid()); } + virtual MiscReg readMiscRegWithEffect(int misc_reg) + { return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); } /** Sets a misc. register. */ - virtual Fault setMiscReg(int misc_reg, const MiscReg &val); + virtual void setMiscReg(int misc_reg, const MiscReg &val); /** Sets a misc. register, including any side-effects the * write might have as defined by the architecture. */ - virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); + virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val); /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 2bc194d53..8d623f5b8 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -194,7 +194,7 @@ void O3ThreadContext<Impl>::regStats(const std::string &name) { #if FULL_SYSTEM - thread->kernelStats = new Kernel::Statistics(cpu->system); + thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); thread->kernelStats->regStats(name + ".kern"); #endif } @@ -439,33 +439,28 @@ O3ThreadContext<Impl>::setNextPC(uint64_t val) } template <class Impl> -Fault +void O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) { - Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid()); + cpu->setMiscReg(misc_reg, val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { cpu->squashFromTC(thread->readTid()); } - - return ret_fault; } template <class Impl> -Fault +void O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, - thread->readTid()); + cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { cpu->squashFromTC(thread->readTid()); } - - return ret_fault; } #if !FULL_SYSTEM diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index 5fe7bb94d..d8720b3ab 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -77,7 +77,7 @@ struct O3ThreadState : public ThreadState { #if FULL_SYSTEM O3ThreadState(O3CPU *_cpu, int _thread_num) - : ThreadState(-1, _thread_num), + : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), inSyscall(0), trapPending(0) { if (cpu->params->profile) { @@ -95,9 +95,8 @@ struct O3ThreadState : public ThreadState { profilePC = 3; } #else - O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid, - MemObject *mem) - : ThreadState(-1, _thread_num, _process, _asid, mem), + O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid) + : ThreadState(_cpu, -1, _thread_num, _process, _asid), cpu(_cpu), inSyscall(0), trapPending(0) { } #endif |