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authorGabe Black <gblack@eecs.umich.edu>2011-08-13 13:36:37 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-08-13 13:36:37 -0700
commite0043f8dbe926ed5bfadb504b0a69b1a1fbfcede (patch)
treeca280844ff12304b869e955a94c9bd830047f70e /src/cpu/o3
parent6bbd74e2d91cab8a1d5a2e340216722f3f249004 (diff)
downloadgem5-e0043f8dbe926ed5bfadb504b0a69b1a1fbfcede.tar.xz
O3: At the end of an instruction, force fetchAddr to something sensible.
It's possible (though until now very unlikely) for fetchAddr to get out of sync with the actual PC of the current instruction. This change forcefull resets fetchAddr at the end of every instruction.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/fetch_impl.hh2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 545969d82..d186768d8 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1342,6 +1342,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
thisPC = nextPC;
if (newMacro) {
+ fetchAddr = thisPC.instAddr() & BaseCPU::PCMask;
+ blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
pcOffset = 0;
curMacroop = NULL;
}