Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

--HG--
extra : convert_revision : f5b6daa2d512f38153246fc9a39cc6560d939ebc

39 files changed, 1488 insertions, 1015 deletions

diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
new file mode 100755
index 000000000..e65d41411
--- /dev/null
+++ b/src/cpu/o3/SConscript
@@ -0,0 +1,79 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+import os
+import os.path
+import sys
+
+# Import build environment variable from SConstruct.
+Import('env')
+
+
+#################################################################
+#
+# Include ISA-specific files for the O3 CPU-model
+#
+#################################################################
+
+sources = []
+
+if env['TARGET_ISA'] == 'alpha':
+    sources += Split('''
+        alpha/dyn_inst.cc
+        alpha/cpu.cc
+        alpha/thread_context.cc
+        alpha/cpu_builder.cc
+        ''')
+elif env['TARGET_ISA'] == 'mips':
+    sys.exit('O3 CPU does not support MIPS')
+    #sources += Split('''
+    #    mips/dyn_inst.cc
+    #    mips/cpu.cc
+    #    mips/thread_context.cc
+    #    mips/cpu_builder.cc
+    #    ''')
+elif env['TARGET_ISA'] == 'sparc':
+    sys.exit('O3 CPU does not support MIPS')
+    #sources += Split('''
+    #    sparc/dyn_inst.cc
+    #    sparc/cpu.cc
+    #    sparc/thread_context.cc
+    #    sparc/cpu_builder.cc
+    #    ''')
+else:
+    sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
+
+
+# Convert file names to SCons File objects.  This takes care of the
+# path relative to the top of the directory tree.
+sources = [File(s) for s in sources]
+
+Return('sources')
+
diff --git a/src/cpu/o3/alpha_cpu.cc b/src/cpu/o3/alpha/cpu.cc
index e44ed0031..ed10b2fd1 100644
--- a/src/cpu/o3/alpha_cpu.cc
+++ b/src/cpu/o3/alpha/cpu.cc
@@ -28,9 +28,9 @@
  * Authors: Kevin Lim
  */
 
-#include "cpu/o3/alpha_impl.hh"
-#include "cpu/o3/alpha_cpu_impl.hh"
-#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha/impl.hh"
+#include "cpu/o3/alpha/cpu_impl.hh"
+#include "cpu/o3/alpha/dyn_inst.hh"
 
 // Force instantiation of AlphaO3CPU for all the implemntations that are
 // needed.  Consider merging this and alpha_dyn_inst.cc, and maybe all
diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
new file mode 100644
index 000000000..b961341d5
--- /dev/null
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
+
+#ifndef __CPU_O3_ALPHA_CPU_HH__
+#define __CPU_O3_ALPHA_CPU_HH__
+
+#include "arch/isa_traits.hh"
+#include "cpu/thread_context.hh"
+#include "cpu/o3/cpu.hh"
+#include "sim/byteswap.hh"
+
+class EndQuiesceEvent;
+namespace Kernel {
+    class Statistics;
+};
+
+class TranslatingPort;
+
+/**
+ * AlphaO3CPU class.  Derives from the FullO3CPU class, and
+ * implements all ISA and implementation specific functions of the
+ * CPU.  This is the CPU class that is used for the SimObjects, and is
+ * what is given to the DynInsts.  Most of its state exists in the
+ * FullO3CPU; the state is has is mainly for ISA specific
+ * functionality.
+ */
+template <class Impl>
+class AlphaO3CPU : public FullO3CPU<Impl>
+{
+  protected:
+    typedef TheISA::IntReg IntReg;
+    typedef TheISA::FloatReg FloatReg;
+    typedef TheISA::FloatRegBits FloatRegBits;
+    typedef TheISA::MiscReg MiscReg;
+    typedef TheISA::RegFile RegFile;
+    typedef TheISA::MiscRegFile MiscRegFile;
+
+  public:
+    typedef O3ThreadState<Impl> ImplState;
+    typedef O3ThreadState<Impl> Thread;
+    typedef typename Impl::Params Params;
+
+    /** Constructs an AlphaO3CPU with the given parameters. */
+    AlphaO3CPU(Params *params);
+
+#if FULL_SYSTEM
+    /** ITB pointer. */
+    AlphaITB *itb;
+    /** DTB pointer. */
+    AlphaDTB *dtb;
+#endif
+
+    /** Registers statistics. */
+    void regStats();
+
+#if FULL_SYSTEM
+    /** Translates instruction requestion. */
+    Fault translateInstReq(RequestPtr &req, Thread *thread)
+    {
+        return itb->translate(req, thread->getTC());
+    }
+
+    /** Translates data read request. */
+    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
+    {
+        return dtb->translate(req, thread->getTC(), false);
+    }
+
+    /** Translates data write request. */
+    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
+    {
+        return dtb->translate(req, thread->getTC(), true);
+    }
+
+#else
+    /** Translates instruction requestion in syscall emulation mode. */
+    Fault translateInstReq(RequestPtr &req, Thread *thread)
+    {
+        return thread->getProcessPtr()->pTable->translate(req);
+    }
+
+    /** Translates data read request in syscall emulation mode. */
+    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
+    {
+        return thread->getProcessPtr()->pTable->translate(req);
+    }
+
+    /** Translates data write request in syscall emulation mode. */
+    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
+    {
+        return thread->getProcessPtr()->pTable->translate(req);
+    }
+
+#endif
+    /** Reads a miscellaneous register. */
+    MiscReg readMiscReg(int misc_reg, unsigned tid);
+
+    /** Reads a misc. register, including any side effects the read
+     * might have as defined by the architecture.
+     */
+    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid);
+
+    /** Sets a miscellaneous register. */
+    Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
+
+    /** Sets a misc. register, including any side effects the write
+     * might have as defined by the architecture.
+     */
+    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
+
+    /** Initiates a squash of all in-flight instructions for a given
+     * thread.  The source of the squash is an external update of
+     * state through the TC.
+     */
+    void squashFromTC(unsigned tid);
+
+#if FULL_SYSTEM
+    /** Posts an interrupt. */
+    void post_interrupt(int int_num, int index);
+    /** Reads the interrupt flag. */
+    int readIntrFlag();
+    /** Sets the interrupt flags. */
+    void setIntrFlag(int val);
+    /** HW return from error interrupt. */
+    Fault hwrei(unsigned tid);
+    /** Returns if a specific PC is a PAL mode PC. */
+    bool inPalMode(uint64_t PC)
+    { return AlphaISA::PcPAL(PC); }
+
+    bool simPalCheck(int palFunc, unsigned tid);
+
+    /** Processes any interrupts. */
+    void processInterrupts();
+
+    /** Halts the CPU. */
+    void halt() { panic("Halt not implemented!\n"); }
+#endif
+
+    /** Traps to handle given fault. */
+    void trap(Fault fault, unsigned tid);
+
+#if !FULL_SYSTEM
+    /** Executes a syscall.
+     * @todo: Determine if this needs to be virtual.
+     */
+    void syscall(int64_t callnum, int tid);
+    /** Gets a syscall argument. */
+    IntReg getSyscallArg(int i, int tid);
+
+    /** Used to shift args for indirect syscall. */
+    void setSyscallArg(int i, IntReg val, int tid);
+
+    /** Sets the return value of a syscall. */
+    void setSyscallReturn(SyscallReturn return_value, int tid);
+#endif
+
+    /** CPU read function, forwards read to LSQ. */
+    template <class T>
+    Fault read(RequestPtr &req, T &data, int load_idx)
+    {
+        return this->iew.ldstQueue.read(req, data, load_idx);
+    }
+
+    /** CPU write function, forwards write to LSQ. */
+    template <class T>
+    Fault write(RequestPtr &req, T &data, int store_idx)
+    {
+        return this->iew.ldstQueue.write(req, data, store_idx);
+    }
+
+    Addr lockAddr;
+
+    /** Temporary fix for the lock flag, works in the UP case. */
+    bool lockFlag;
+};
+
+#endif // __CPU_O3_ALPHA_CPU_HH__
diff --git a/src/cpu/o3/alpha_cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index b1e141ff4..490305cbf 100644
--- a/src/cpu/o3/alpha_cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -31,21 +31,21 @@
 #include <string>
 
 #include "cpu/base.hh"
-#include "cpu/o3/alpha_cpu.hh"
-#include "cpu/o3/alpha_impl.hh"
-#include "cpu/o3/alpha_params.hh"
+#include "cpu/o3/alpha/cpu.hh"
+#include "cpu/o3/alpha/impl.hh"
+#include "cpu/o3/alpha/params.hh"
 #include "cpu/o3/fu_pool.hh"
 #include "sim/builder.hh"
 
-class DerivAlphaO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
+class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
 {
   public:
-    DerivAlphaO3CPU(AlphaSimpleParams *p)
+    DerivO3CPU(AlphaSimpleParams *p)
         : AlphaO3CPU<AlphaSimpleImpl>(p)
     { }
 };
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaO3CPU)
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
 
     Param<int> clock;
     Param<int> numThreads;
@@ -144,9 +144,9 @@ Param<bool> defer_registration;
 Param<bool> function_trace;
 Param<Tick> function_trace_start;
 
-END_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaO3CPU)
+END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
 
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaO3CPU)
+BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
 
     INIT_PARAM(clock, "clock speed"),
     INIT_PARAM(numThreads, "number of HW thread contexts"),
@@ -261,11 +261,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaO3CPU)
     INIT_PARAM(function_trace, "Enable function trace"),
     INIT_PARAM(function_trace_start, "Cycle to start function trace")
 
-END_INIT_SIM_OBJECT_PARAMS(DerivAlphaO3CPU)
+END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
 
-CREATE_SIM_OBJECT(DerivAlphaO3CPU)
+CREATE_SIM_OBJECT(DerivO3CPU)
 {
-    DerivAlphaO3CPU *cpu;
+    DerivO3CPU *cpu;
 
 #if FULL_SYSTEM
     // Full-system only supports a single thread for the moment.
@@ -274,12 +274,12 @@ CREATE_SIM_OBJECT(DerivAlphaO3CPU)
     // In non-full-system mode, we infer the number of threads from
     // the workload if it's not explicitly specified.
     int actual_num_threads =
-        numThreads.isValid() ? numThreads : workload.size();
+        (numThreads.isValid() && numThreads >= workload.size()) ?
+         numThreads : workload.size();
 
     if (workload.size() == 0) {
         fatal("Must specify at least one workload!");
     }
-
 #endif
 
     AlphaSimpleParams *params = new AlphaSimpleParams;
@@ -371,7 +371,16 @@ CREATE_SIM_OBJECT(DerivAlphaO3CPU)
     params->numROBEntries = numROBEntries;
 
     params->smtNumFetchingThreads = smtNumFetchingThreads;
-    params->smtFetchPolicy = smtFetchPolicy;
+
+    // Default smtFetchPolicy to "RoundRobin", if necessary.
+    std::string round_robin_policy = "RoundRobin";
+    std::string single_thread = "SingleThread";
+
+    if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
+        params->smtFetchPolicy = round_robin_policy;
+    else
+        params->smtFetchPolicy = smtFetchPolicy;
+
     params->smtIQPolicy    = smtIQPolicy;
     params->smtLSQPolicy    = smtLSQPolicy;
     params->smtLSQThreshold = smtLSQThreshold;
@@ -386,10 +395,10 @@ CREATE_SIM_OBJECT(DerivAlphaO3CPU)
     params->functionTrace = function_trace;
     params->functionTraceStart = function_trace_start;
 
-    cpu = new DerivAlphaO3CPU(params);
+    cpu = new DerivO3CPU(params);
 
     return cpu;
 }
 
-REGISTER_SIM_OBJECT("DerivAlphaO3CPU", DerivAlphaO3CPU)
+REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
 
diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index eca6fbbcb..0473e60c2 100644
--- a/src/cpu/o3/alpha_cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -38,8 +38,9 @@
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
 
-#include "cpu/o3/alpha_cpu.hh"
-#include "cpu/o3/alpha_params.hh"
+#include "cpu/o3/alpha/cpu.hh"
+#include "cpu/o3/alpha/params.hh"
+#include "cpu/o3/alpha/thread_context.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/thread_state.hh"
 
@@ -110,7 +111,8 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
         ThreadContext *tc;
 
         // Setup the TC that will serve as the interface to the threads/CPU.
-        AlphaTC *alpha_tc = new AlphaTC;
+        AlphaTC<Impl> *alpha_tc =
+            new AlphaTC<Impl>;
 
         tc = alpha_tc;
 
@@ -118,7 +120,7 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
         // CheckerThreadContext.
 #if USE_CHECKER
         if (params->checker) {
-            tc = new CheckerThreadContext<AlphaTC>(
+            tc = new CheckerThreadContext<AlphaTC<Impl> >(
                 alpha_tc, this->checker);
         }
 #endif
@@ -187,465 +189,6 @@ AlphaO3CPU<Impl>::regStats()
     this->commit.regStats();
 }
 
-#if FULL_SYSTEM
-template <class Impl>
-VirtualPort *
-AlphaO3CPU<Impl>::AlphaTC::getVirtPort(ThreadContext *src_tc)
-{
-    if (!src_tc)
-        return thread->getVirtPort();
-
-    VirtualPort *vp;
-    Port *mem_port;
-
-    vp = new VirtualPort("tc-vport", src_tc);
-    mem_port = cpu->system->physmem->getPort("functional");
-    mem_port->setPeer(vp);
-    vp->setPeer(mem_port);
-    return vp;
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::dumpFuncProfile()
-{
-    // Currently not supported
-}
-#endif
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::takeOverFrom(ThreadContext *old_context)
-{
-    // some things should already be set up
-#if FULL_SYSTEM
-    assert(getSystemPtr() == old_context->getSystemPtr());
-#else
-    assert(getProcessPtr() == old_context->getProcessPtr());
-#endif
-
-    // copy over functional state
-    setStatus(old_context->status());
-    copyArchRegs(old_context);
-    setCpuId(old_context->readCpuId());
-
-#if !FULL_SYSTEM
-    thread->funcExeInst = old_context->readFuncExeInst();
-#else
-    EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
-    if (other_quiesce) {
-        // Point the quiesce event's TC at this TC so that it wakes up
-        // the proper CPU.
-        other_quiesce->tc = this;
-    }
-    if (thread->quiesceEvent) {
-        thread->quiesceEvent->tc = this;
-    }
-
-    // Transfer kernel stats from one CPU to the other.
-    thread->kernelStats = old_context->getKernelStats();
-//    storeCondFailures = 0;
-    cpu->lockFlag = false;
-#endif
-
-    old_context->setStatus(ThreadContext::Unallocated);
-
-    thread->inSyscall = false;
-    thread->trapPending = false;
-}
-
-#if FULL_SYSTEM
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::delVirtPort(VirtualPort *vp)
-{
-    delete vp->getPeer();
-    delete vp;
-}
-#endif
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::activate(int delay)
-{
-    DPRINTF(O3CPU, "Calling activate on AlphaTC\n");
-
-    if (thread->status() == ThreadContext::Active)
-        return;
-
-#if FULL_SYSTEM
-    thread->lastActivate = curTick;
-#endif
-
-    if (thread->status() == ThreadContext::Unallocated) {
-        cpu->activateWhenReady(thread->readTid());
-        return;
-    }
-
-    thread->setStatus(ThreadContext::Active);
-
-    // status() == Suspended
-    cpu->activateContext(thread->readTid(), delay);
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::suspend()
-{
-    DPRINTF(O3CPU, "Calling suspend on AlphaTC\n");
-
-    if (thread->status() == ThreadContext::Suspended)
-        return;
-
-#if FULL_SYSTEM
-    thread->lastActivate = curTick;
-    thread->lastSuspend = curTick;
-#endif
-/*
-#if FULL_SYSTEM
-    // Don't change the status from active if there are pending interrupts
-    if (cpu->check_interrupts()) {
-        assert(status() == ThreadContext::Active);
-        return;
-    }
-#endif
-*/
-    thread->setStatus(ThreadContext::Suspended);
-    cpu->suspendContext(thread->readTid());
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::deallocate()
-{
-    DPRINTF(O3CPU, "Calling deallocate on AlphaTC\n");
-
-    if (thread->status() == ThreadContext::Unallocated)
-        return;
-
-    thread->setStatus(ThreadContext::Unallocated);
-    cpu->deallocateContext(thread->readTid());
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::halt()
-{
-    DPRINTF(O3CPU, "Calling halt on AlphaTC\n");
-
-    if (thread->status() == ThreadContext::Halted)
-        return;
-
-    thread->setStatus(ThreadContext::Halted);
-    cpu->haltContext(thread->readTid());
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::regStats(const std::string &name)
-{
-#if FULL_SYSTEM
-    thread->kernelStats = new Kernel::Statistics(cpu->system);
-    thread->kernelStats->regStats(name + ".kern");
-#endif
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::serialize(std::ostream &os)
-{
-#if FULL_SYSTEM
-    if (thread->kernelStats)
-        thread->kernelStats->serialize(os);
-#endif
-
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::unserialize(Checkpoint *cp, const std::string &section)
-{
-#if FULL_SYSTEM
-    if (thread->kernelStats)
-        thread->kernelStats->unserialize(cp, section);
-#endif
-
-}
-
-#if FULL_SYSTEM
-template <class Impl>
-EndQuiesceEvent *
-AlphaO3CPU<Impl>::AlphaTC::getQuiesceEvent()
-{
-    return thread->quiesceEvent;
-}
-
-template <class Impl>
-Tick
-AlphaO3CPU<Impl>::AlphaTC::readLastActivate()
-{
-    return thread->lastActivate;
-}
-
-template <class Impl>
-Tick
-AlphaO3CPU<Impl>::AlphaTC::readLastSuspend()
-{
-    return thread->lastSuspend;
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::profileClear()
-{}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::profileSample()
-{}
-#endif
-
-template <class Impl>
-TheISA::MachInst
-AlphaO3CPU<Impl>::AlphaTC:: getInst()
-{
-    return thread->getInst();
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::copyArchRegs(ThreadContext *tc)
-{
-    // This function will mess things up unless the ROB is empty and
-    // there are no instructions in the pipeline.
-    unsigned tid = thread->readTid();
-    PhysRegIndex renamed_reg;
-
-    // First loop through the integer registers.
-    for (int i = 0; i < AlphaISA::NumIntRegs; ++i) {
-        renamed_reg = cpu->renameMap[tid].lookup(i);
-
-        DPRINTF(O3CPU, "Copying over register %i, had data %lli, "
-                "now has data %lli.\n",
-                renamed_reg, cpu->readIntReg(renamed_reg),
-                tc->readIntReg(i));
-
-        cpu->setIntReg(renamed_reg, tc->readIntReg(i));
-    }
-
-    // Then loop through the floating point registers.
-    for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) {
-        renamed_reg = cpu->renameMap[tid].lookup(i + AlphaISA::FP_Base_DepTag);
-        cpu->setFloatRegBits(renamed_reg,
-                             tc->readFloatRegBits(i));
-    }
-
-    // Copy the misc regs.
-    copyMiscRegs(tc, this);
-
-    // Then finally set the PC and the next PC.
-    cpu->setPC(tc->readPC(), tid);
-    cpu->setNextPC(tc->readNextPC(), tid);
-#if !FULL_SYSTEM
-    this->thread->funcExeInst = tc->readFuncExeInst();
-#endif
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::clearArchRegs()
-{}
-
-template <class Impl>
-uint64_t
-AlphaO3CPU<Impl>::AlphaTC::readIntReg(int reg_idx)
-{
-    return cpu->readArchIntReg(reg_idx, thread->readTid());
-}
-
-template <class Impl>
-FloatReg
-AlphaO3CPU<Impl>::AlphaTC::readFloatReg(int reg_idx, int width)
-{
-    switch(width) {
-      case 32:
-        return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
-      case 64:
-        return cpu->readArchFloatRegDouble(reg_idx, thread->readTid());
-      default:
-        panic("Unsupported width!");
-        return 0;
-    }
-}
-
-template <class Impl>
-FloatReg
-AlphaO3CPU<Impl>::AlphaTC::readFloatReg(int reg_idx)
-{
-    return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
-}
-
-template <class Impl>
-FloatRegBits
-AlphaO3CPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx, int width)
-{
-    DPRINTF(Fault, "Reading floatint register through the TC!\n");
-    return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
-}
-
-template <class Impl>
-FloatRegBits
-AlphaO3CPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx)
-{
-    return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::setIntReg(int reg_idx, uint64_t val)
-{
-    cpu->setArchIntReg(reg_idx, val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
-    }
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width)
-{
-    switch(width) {
-      case 32:
-        cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
-        break;
-      case 64:
-        cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid());
-        break;
-    }
-
-    // Squash if we're not already in a state update mode.
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
-    }
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val)
-{
-    cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
-
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
-    }
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val,
-                                             int width)
-{
-    DPRINTF(Fault, "Setting floatint register through the TC!\n");
-    cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
-    }
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val)
-{
-    cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
-    }
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::setPC(uint64_t val)
-{
-    cpu->setPC(val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
-    }
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::setNextPC(uint64_t val)
-{
-    cpu->setNextPC(val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
-    }
-}
-
-template <class Impl>
-Fault
-AlphaO3CPU<Impl>::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val)
-{
-    Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
-    }
-
-    return ret_fault;
-}
-
-template <class Impl>
-Fault
-AlphaO3CPU<Impl>::AlphaTC::setMiscRegWithEffect(int misc_reg,
-                                                const MiscReg &val)
-{
-    Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val,
-                                                thread->readTid());
-
-    // Squash if we're not already in a state update mode.
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->readTid());
-    }
-
-    return ret_fault;
-}
-
-#if !FULL_SYSTEM
-
-template <class Impl>
-TheISA::IntReg
-AlphaO3CPU<Impl>::AlphaTC::getSyscallArg(int i)
-{
-    return cpu->getSyscallArg(i, thread->readTid());
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::setSyscallArg(int i, IntReg val)
-{
-    cpu->setSyscallArg(i, val, thread->readTid());
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::AlphaTC::setSyscallReturn(SyscallReturn return_value)
-{
-    cpu->setSyscallReturn(return_value, thread->readTid());
-}
-
-#endif // FULL_SYSTEM
 
 template <class Impl>
 MiscReg
diff --git a/src/cpu/o3/alpha_dyn_inst.cc b/src/cpu/o3/alpha/dyn_inst.cc
index 0c1723eec..97d2f3d08 100644
--- a/src/cpu/o3/alpha_dyn_inst.cc
+++ b/src/cpu/o3/alpha/dyn_inst.cc
@@ -28,8 +28,8 @@
  * Authors: Kevin Lim
  */
 
-#include "cpu/o3/alpha_dyn_inst_impl.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/alpha/dyn_inst_impl.hh"
+#include "cpu/o3/alpha/impl.hh"
 
 // Force instantiation of AlphaDynInst for all the implementations that
 // are needed.
diff --git a/src/cpu/o3/alpha_dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 464e53e9d..9dee610b6 100644
--- a/src/cpu/o3/alpha_dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -34,8 +34,8 @@
 #include "arch/isa_traits.hh"
 #include "cpu/base_dyn_inst.hh"
 #include "cpu/inst_seq.hh"
-#include "cpu/o3/alpha_cpu.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/alpha/cpu.hh"
+#include "cpu/o3/alpha/impl.hh"
 
 class Packet;
 
diff --git a/src/cpu/o3/alpha_dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh
index 855ee9963..2d1b4b309 100644
--- a/src/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha/dyn_inst_impl.hh
@@ -28,7 +28,7 @@
  * Authors: Kevin Lim
  */
 
-#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha/dyn_inst.hh"
 
 template <class Impl>
 AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
diff --git a/src/cpu/o3/alpha_impl.hh b/src/cpu/o3/alpha/impl.hh
index 84c9e1c00..8cd8692c6 100644
--- a/src/cpu/o3/alpha_impl.hh
+++ b/src/cpu/o3/alpha/impl.hh
@@ -33,7 +33,7 @@
 
 #include "arch/alpha/isa_traits.hh"
 
-#include "cpu/o3/alpha_params.hh"
+#include "cpu/o3/alpha/params.hh"
 #include "cpu/o3/cpu_policy.hh"
 
 // Forward declarations.
@@ -85,4 +85,10 @@ struct AlphaSimpleImpl
     };
 };
 
+/** The O3Impl to be used. */
+typedef AlphaSimpleImpl O3CPUImpl;
+
+/** The O3Impl to be used. */
+typedef DynInst O3DynInst;
+
 #endif // __CPU_O3_ALPHA_IMPL_HH__
diff --git a/src/cpu/o3/alpha/params.hh b/src/cpu/o3/alpha/params.hh
new file mode 100644
index 000000000..b1f2a487d
--- /dev/null
+++ b/src/cpu/o3/alpha/params.hh
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
+
+#ifndef __CPU_O3_ALPHA_PARAMS_HH__
+#define __CPU_O3_ALPHA_PARAMS_HH__
+
+#include "cpu/o3/cpu.hh"
+#include "cpu/o3/params.hh"
+
+//Forward declarations
+class AlphaDTB;
+class AlphaITB;
+class MemObject;
+class Process;
+class System;
+
+/**
+ * This file defines the parameters that will be used for the AlphaO3CPU.
+ * This must be defined externally so that the Impl can have a params class
+ * defined that it can pass to all of the individual stages.
+ */
+
+class AlphaSimpleParams : public O3Params
+{
+  public:
+
+#if FULL_SYSTEM
+    AlphaITB *itb;
+    AlphaDTB *dtb;
+#else
+    std::vector<Process *> workload;
+    Process *process;
+#endif // FULL_SYSTEM
+
+    MemObject *mem;
+
+    BaseCPU *checker;
+
+    unsigned decodeToFetchDelay;
+};
+
+#endif // __CPU_O3_ALPHA_PARAMS_HH__
diff --git a/src/cpu/o3/alpha/thread_context.cc b/src/cpu/o3/alpha/thread_context.cc
new file mode 100755
index 000000000..4a02715bc
--- /dev/null
+++ b/src/cpu/o3/alpha/thread_context.cc
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ *          Korey Sewell
+ */
+
+#include "cpu/o3/thread_context.hh"
+#include "cpu/o3/thread_context_impl.hh"
+
+template class O3ThreadContext<AlphaSimpleImpl>;
+
diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh
new file mode 100644
index 000000000..78b0ee788
--- /dev/null
+++ b/src/cpu/o3/alpha/thread_context.hh
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ *          Korey Sewell
+ */
+
+#include "cpu/o3/thread_context.hh"
+
+template <class Impl>
+class AlphaTC : public O3ThreadContext<Impl>
+{
+  public:
+#if FULL_SYSTEM
+    /** Returns a pointer to the ITB. */
+    virtual AlphaITB *getITBPtr() { return this->cpu->itb; }
+
+    /** Returns a pointer to the DTB. */
+    virtual AlphaDTB *getDTBPtr() { return this->cpu->dtb; }
+
+    /** Returns pointer to the quiesce event. */
+    virtual EndQuiesceEvent *getQuiesceEvent()
+    {
+        return this->thread->quiesceEvent;
+    }
+
+    /** Returns if the thread is currently in PAL mode, based on
+     * the PC's value. */
+    virtual bool inPalMode()
+    { return TheISA::PcPAL(this->cpu->readPC(this->thread->readTid())); }
+#endif
+
+    virtual uint64_t readNextNPC()
+    {
+        panic("Alpha has no NextNPC!");
+        return 0;
+    }
+
+    virtual void setNextNPC(uint64_t val)
+    {
+        panic("Alpha has no NextNPC!");
+    }
+
+    virtual void changeRegFileContext(TheISA::RegFile::ContextParam param,
+                                      TheISA::RegFile::ContextVal val)
+    { panic("Not supported on Alpha!"); }
+
+
+    // This function exits the thread context in the CPU and returns
+    // 1 if the CPU has no more active threads (meaning it's OK to exit);
+    // Used in syscall-emulation mode when a thread executes the 'exit'
+    // syscall.
+    virtual int exit()
+    {
+        this->cpu->deallocateContext(this->thread->readTid());
+
+        // If there are still threads executing in the system
+        if (this->cpu->numActiveThreads())
+            return 0;
+        else
+            return 1;
+    }
+};
diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh
deleted file mode 100644
index d7f3d5801..000000000
--- a/src/cpu/o3/alpha_cpu.hh
+++ /dev/null
@@ -1,434 +0,0 @@
-/*
- * Copyright (c) 2004-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#ifndef __CPU_O3_ALPHA_CPU_HH__
-#define __CPU_O3_ALPHA_CPU_HH__
-
-#include "arch/isa_traits.hh"
-#include "cpu/thread_context.hh"
-#include "cpu/o3/cpu.hh"
-#include "sim/byteswap.hh"
-
-class EndQuiesceEvent;
-namespace Kernel {
-    class Statistics;
-};
-
-class TranslatingPort;
-
-/**
- * AlphaO3CPU class.  Derives from the FullO3CPU class, and
- * implements all ISA and implementation specific functions of the
- * CPU.  This is the CPU class that is used for the SimObjects, and is
- * what is given to the DynInsts.  Most of its state exists in the
- * FullO3CPU; the state is has is mainly for ISA specific
- * functionality.
- */
-template <class Impl>
-class AlphaO3CPU : public FullO3CPU<Impl>
-{
-  protected:
-    typedef TheISA::IntReg IntReg;
-    typedef TheISA::FloatReg FloatReg;
-    typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscReg MiscReg;
-    typedef TheISA::RegFile RegFile;
-    typedef TheISA::MiscRegFile MiscRegFile;
-
-  public:
-    typedef O3ThreadState<Impl> ImplState;
-    typedef O3ThreadState<Impl> Thread;
-    typedef typename Impl::Params Params;
-
-    /** Constructs an AlphaO3CPU with the given parameters. */
-    AlphaO3CPU(Params *params);
-
-    /**
-     * Derived ThreadContext class for use with the AlphaO3CPU.  It
-     * provides the interface for any external objects to access a
-     * single thread's state and some general CPU state.  Any time
-     * external objects try to update state through this interface,
-     * the CPU will create an event to squash all in-flight
-     * instructions in order to ensure state is maintained correctly.
-     * It must be defined specifically for the AlphaO3CPU because
-     * not all architectural state is located within the O3ThreadState
-     * (such as the commit PC, and registers), and specific actions
-     * must be taken when using this interface (such as squashing all
-     * in-flight instructions when doing a write to this interface).
-     */
-    class AlphaTC : public ThreadContext
-    {
-      public:
-        /** Pointer to the CPU. */
-        AlphaO3CPU<Impl> *cpu;
-
-        /** Pointer to the thread state that this TC corrseponds to. */
-        O3ThreadState<Impl> *thread;
-
-        /** Returns a pointer to this CPU. */
-        virtual BaseCPU *getCpuPtr() { return cpu; }
-
-        /** Sets this CPU's ID. */
-        virtual void setCpuId(int id) { cpu->cpu_id = id; }
-
-        /** Reads this CPU's ID. */
-        virtual int readCpuId() { return cpu->cpu_id; }
-
-#if FULL_SYSTEM
-        /** Returns a pointer to the system. */
-        virtual System *getSystemPtr() { return cpu->system; }
-
-        /** Returns a pointer to physical memory. */
-        virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
-
-        /** Returns a pointer to the ITB. */
-        virtual AlphaITB *getITBPtr() { return cpu->itb; }
-
-        /** Returns a pointer to the DTB. */
-        virtual AlphaDTB *getDTBPtr() { return cpu->dtb; }
-
-        /** Returns a pointer to this thread's kernel statistics. */
-        virtual Kernel::Statistics *getKernelStats()
-        { return thread->kernelStats; }
-
-        virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
-
-        virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL);
-
-        void delVirtPort(VirtualPort *vp);
-#else
-        virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
-
-        /** Returns a pointer to this thread's process. */
-        virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
-#endif
-        /** Returns this thread's status. */
-        virtual Status status() const { return thread->status(); }
-
-        /** Sets this thread's status. */
-        virtual void setStatus(Status new_status)
-        { thread->setStatus(new_status); }
-
-        /** Set the status to Active.  Optional delay indicates number of
-         * cycles to wait before beginning execution. */
-        virtual void activate(int delay = 1);
-
-        /** Set the status to Suspended. */
-        virtual void suspend();
-
-        /** Set the status to Unallocated. */
-        virtual void deallocate();
-
-        /** Set the status to Halted. */
-        virtual void halt();
-
-#if FULL_SYSTEM
-        /** Dumps the function profiling information.
-         * @todo: Implement.
-         */
-        virtual void dumpFuncProfile();
-#endif
-        /** Takes over execution of a thread from another CPU. */
-        virtual void takeOverFrom(ThreadContext *old_context);
-
-        /** Registers statistics associated with this TC. */
-        virtual void regStats(const std::string &name);
-
-        /** Serializes state. */
-        virtual void serialize(std::ostream &os);
-        /** Unserializes state. */
-        virtual void unserialize(Checkpoint *cp, const std::string &section);
-
-#if FULL_SYSTEM
-        /** Returns pointer to the quiesce event. */
-        virtual EndQuiesceEvent *getQuiesceEvent();
-
-        /** Reads the last tick that this thread was activated on. */
-        virtual Tick readLastActivate();
-        /** Reads the last tick that this thread was suspended on. */
-        virtual Tick readLastSuspend();
-
-        /** Clears the function profiling information. */
-        virtual void profileClear();
-        /** Samples the function profiling information. */
-        virtual void profileSample();
-#endif
-        /** Returns this thread's ID number. */
-        virtual int getThreadNum() { return thread->readTid(); }
-
-        /** Returns the instruction this thread is currently committing.
-         *  Only used when an instruction faults.
-         */
-        virtual TheISA::MachInst getInst();
-
-        /** Copies the architectural registers from another TC into this TC. */
-        virtual void copyArchRegs(ThreadContext *tc);
-
-        /** Resets all architectural registers to 0. */
-        virtual void clearArchRegs();
-
-        /** Reads an integer register. */
-        virtual uint64_t readIntReg(int reg_idx);
-
-        virtual FloatReg readFloatReg(int reg_idx, int width);
-
-        virtual FloatReg readFloatReg(int reg_idx);
-
-        virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
-
-        virtual FloatRegBits readFloatRegBits(int reg_idx);
-
-        /** Sets an integer register to a value. */
-        virtual void setIntReg(int reg_idx, uint64_t val);
-
-        virtual void setFloatReg(int reg_idx, FloatReg val, int width);
-
-        virtual void setFloatReg(int reg_idx, FloatReg val);
-
-        virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
-
-        virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
-
-        /** Reads this thread's PC. */
-        virtual uint64_t readPC()
-        { return cpu->readPC(thread->readTid()); }
-
-        /** Sets this thread's PC. */
-        virtual void setPC(uint64_t val);
-
-        /** Reads this thread's next PC. */
-        virtual uint64_t readNextPC()
-        { return cpu->readNextPC(thread->readTid()); }
-
-        /** Sets this thread's next PC. */
-        virtual void setNextPC(uint64_t val);
-
-        virtual uint64_t readNextNPC()
-        {
-            panic("Alpha has no NextNPC!");
-            return 0;
-        }
-
-        virtual void setNextNPC(uint64_t val)
-        { }
-
-        /** Reads a miscellaneous register. */
-        virtual MiscReg readMiscReg(int misc_reg)
-        { return cpu->readMiscReg(misc_reg, thread->readTid()); }
-
-        /** Reads a misc. register, including any side-effects the
-         * read might have as defined by the architecture. */
-        virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
-        { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->readTid()); }
-
-        /** Sets a misc. register. */
-        virtual Fault setMiscReg(int misc_reg, const MiscReg &val);
-
-        /** Sets a misc. register, including any side-effects the
-         * write might have as defined by the architecture. */
-        virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
-
-        /** Returns the number of consecutive store conditional failures. */
-        // @todo: Figure out where these store cond failures should go.
-        virtual unsigned readStCondFailures()
-        { return thread->storeCondFailures; }
-
-        /** Sets the number of consecutive store conditional failures. */
-        virtual void setStCondFailures(unsigned sc_failures)
-        { thread->storeCondFailures = sc_failures; }
-
-#if FULL_SYSTEM
-        /** Returns if the thread is currently in PAL mode, based on
-         * the PC's value. */
-        virtual bool inPalMode()
-        { return TheISA::PcPAL(cpu->readPC(thread->readTid())); }
-#endif
-        // Only really makes sense for old CPU model.  Lots of code
-        // outside the CPU still checks this function, so it will
-        // always return false to keep everything working.
-        /** Checks if the thread is misspeculating.  Because it is
-         * very difficult to determine if the thread is
-         * misspeculating, this is set as false. */
-        virtual bool misspeculating() { return false; }
-
-#if !FULL_SYSTEM
-        /** Gets a syscall argument by index. */
-        virtual IntReg getSyscallArg(int i);
-
-        /** Sets a syscall argument. */
-        virtual void setSyscallArg(int i, IntReg val);
-
-        /** Sets the syscall return value. */
-        virtual void setSyscallReturn(SyscallReturn return_value);
-
-        /** Executes a syscall in SE mode. */
-        virtual void syscall(int64_t callnum)
-        { return cpu->syscall(callnum, thread->readTid()); }
-
-        /** Reads the funcExeInst counter. */
-        virtual Counter readFuncExeInst() { return thread->funcExeInst; }
-#endif
-        virtual void changeRegFileContext(TheISA::RegFile::ContextParam param,
-                                          TheISA::RegFile::ContextVal val)
-        { panic("Not supported on Alpha!"); }
-    };
-
-#if FULL_SYSTEM
-    /** ITB pointer. */
-    AlphaITB *itb;
-    /** DTB pointer. */
-    AlphaDTB *dtb;
-#endif
-
-    /** Registers statistics. */
-    void regStats();
-
-#if FULL_SYSTEM
-    /** Translates instruction requestion. */
-    Fault translateInstReq(RequestPtr &req, Thread *thread)
-    {
-        return itb->translate(req, thread->getTC());
-    }
-
-    /** Translates data read request. */
-    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
-    {
-        return dtb->translate(req, thread->getTC(), false);
-    }
-
-    /** Translates data write request. */
-    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
-    {
-        return dtb->translate(req, thread->getTC(), true);
-    }
-
-#else
-    /** Translates instruction requestion in syscall emulation mode. */
-    Fault translateInstReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-    /** Translates data read request in syscall emulation mode. */
-    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-    /** Translates data write request in syscall emulation mode. */
-    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-#endif
-    /** Reads a miscellaneous register. */
-    MiscReg readMiscReg(int misc_reg, unsigned tid);
-
-    /** Reads a misc. register, including any side effects the read
-     * might have as defined by the architecture.
-     */
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid);
-
-    /** Sets a miscellaneous register. */
-    Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
-
-    /** Sets a misc. register, including any side effects the write
-     * might have as defined by the architecture.
-     */
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
-
-    /** Initiates a squash of all in-flight instructions for a given
-     * thread.  The source of the squash is an external update of
-     * state through the TC.
-     */
-    void squashFromTC(unsigned tid);
-
-#if FULL_SYSTEM
-    /** Posts an interrupt. */
-    void post_interrupt(int int_num, int index);
-    /** Reads the interrupt flag. */
-    int readIntrFlag();
-    /** Sets the interrupt flags. */
-    void setIntrFlag(int val);
-    /** HW return from error interrupt. */
-    Fault hwrei(unsigned tid);
-    /** Returns if a specific PC is a PAL mode PC. */
-    bool inPalMode(uint64_t PC)
-    { return AlphaISA::PcPAL(PC); }
-
-    bool simPalCheck(int palFunc, unsigned tid);
-
-    /** Processes any interrupts. */
-    void processInterrupts();
-
-    /** Halts the CPU. */
-    void halt() { panic("Halt not implemented!\n"); }
-#endif
-
-    /** Traps to handle given fault. */
-    void trap(Fault fault, unsigned tid);
-
-#if !FULL_SYSTEM
-    /** Executes a syscall.
-     * @todo: Determine if this needs to be virtual.
-     */
-    void syscall(int64_t callnum, int tid);
-    /** Gets a syscall argument. */
-    IntReg getSyscallArg(int i, int tid);
-
-    /** Used to shift args for indirect syscall. */
-    void setSyscallArg(int i, IntReg val, int tid);
-
-    /** Sets the return value of a syscall. */
-    void setSyscallReturn(SyscallReturn return_value, int tid);
-#endif
-
-    /** CPU read function, forwards read to LSQ. */
-    template <class T>
-    Fault read(RequestPtr &req, T &data, int load_idx)
-    {
-        return this->iew.ldstQueue.read(req, data, load_idx);
-    }
-
-    /** CPU write function, forwards write to LSQ. */
-    template <class T>
-    Fault write(RequestPtr &req, T &data, int store_idx)
-    {
-        return this->iew.ldstQueue.write(req, data, store_idx);
-    }
-
-    Addr lockAddr;
-
-    /** Temporary fix for the lock flag, works in the UP case. */
-    bool lockFlag;
-};
-
-#endif // __CPU_O3_ALPHA_CPU_HH__
diff --git a/src/cpu/o3/base_dyn_inst.cc b/src/cpu/o3/base_dyn_inst.cc
index 1f7540d6a..0979c5c8f 100644
--- a/src/cpu/o3/base_dyn_inst.cc
+++ b/src/cpu/o3/base_dyn_inst.cc
@@ -29,12 +29,11 @@
  */
 
 #include "cpu/base_dyn_inst_impl.hh"
-#include "cpu/o3/alpha_cpu.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/isa_specific.hh"
 
 // Explicit instantiation
-template class BaseDynInst<AlphaSimpleImpl>;
+template class BaseDynInst<O3CPUImpl>;
 
 template <>
 int
-BaseDynInst<AlphaSimpleImpl>::instcount = 0;
+BaseDynInst<O3CPUImpl>::instcount = 0;
diff --git a/src/cpu/o3/bpred_unit.cc b/src/cpu/o3/bpred_unit.cc
index c35c0a0aa..08fd4e8ea 100644
--- a/src/cpu/o3/bpred_unit.cc
+++ b/src/cpu/o3/bpred_unit.cc
@@ -29,7 +29,6 @@
  */
 
 #include "cpu/o3/bpred_unit_impl.hh"
-#include "cpu/o3/alpha_impl.hh"
-#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/isa_specific.hh"
 
-template class BPredUnit<AlphaSimpleImpl>;
+template class BPredUnit<O3CPUImpl>;
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index 58c40d00c..782d963b0 100644
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -32,8 +32,8 @@
 
 #include "cpu/checker/cpu_impl.hh"
 #include "cpu/inst_seq.hh"
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/alpha/dyn_inst.hh"
+#include "cpu/o3/alpha/impl.hh"
 #include "sim/builder.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"
diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc
index 770008a33..637d59f52 100644
--- a/src/cpu/o3/commit.cc
+++ b/src/cpu/o3/commit.cc
@@ -28,8 +28,7 @@
  * Authors: Kevin Lim
  */
 
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/commit_impl.hh"
 
-template class DefaultCommit<AlphaSimpleImpl>;
+template class DefaultCommit<O3CPUImpl>;
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 860326283..60b555269 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -406,8 +406,10 @@ class DefaultCommit
     /** The next PC of each thread. */
     Addr nextPC[Impl::MaxThreads];
 
+#if THE_ISA != ALPHA_ISA
     /** The next NPC of each thread. */
     Addr nextNPC[Impl::MaxThreads];
+#endif
 
     /** The sequence number of the youngest valid instruction in the ROB. */
     InstSeqNum youngestSeqNum[Impl::MaxThreads];
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index cd7dd47d4..06b8e8a95 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1221,7 +1221,8 @@ DefaultCommit<Impl>::roundRobin()
         unsigned tid = *pri_iter;
 
         if (commitStatus[tid] == Running ||
-            commitStatus[tid] == Idle) {
+            commitStatus[tid] == Idle ||
+            commitStatus[tid] == FetchTrapPending) {
 
             if (rob->isHeadReady(tid)) {
                 priority_list.erase(pri_iter);
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 553399048..feca4cdf2 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -41,8 +41,7 @@
 #include "cpu/activity.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/cpu.hh"
 
 #include "sim/root.hh"
@@ -87,6 +86,35 @@ FullO3CPU<Impl>::TickEvent::description()
 }
 
 template <class Impl>
+FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
+    : Event(&mainEventQueue, CPU_Tick_Pri)
+{
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
+                                           FullO3CPU<Impl> *thread_cpu)
+{
+    tid = thread_num;
+    cpu = thread_cpu;
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::ActivateThreadEvent::process()
+{
+    cpu->activateThread(tid);
+}
+
+template <class Impl>
+const char *
+FullO3CPU<Impl>::ActivateThreadEvent::description()
+{
+    return "FullO3CPU \"Activate Thread\" event";
+}
+
+template <class Impl>
 FullO3CPU<Impl>::FullO3CPU(Params *params)
     : BaseO3CPU(params),
       tickEvent(this),
@@ -99,7 +127,7 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
 
       regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
 
-      freeList(params->numberOfThreads,//number of activeThreads
+      freeList(params->numberOfThreads,
                TheISA::NumIntRegs, params->numPhysIntRegs,
                TheISA::NumFloatRegs, params->numPhysFloatRegs),
 
@@ -107,7 +135,7 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
           params->smtROBPolicy, params->smtROBThreshold,
           params->numberOfThreads),
 
-      scoreboard(params->numberOfThreads,//number of activeThreads
+      scoreboard(params->numberOfThreads,
                  TheISA::NumIntRegs, params->numPhysIntRegs,
                  TheISA::NumFloatRegs, params->numPhysFloatRegs,
                  TheISA::NumMiscRegs * number_of_threads,
@@ -193,6 +221,12 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
 
 #if !FULL_SYSTEM
     int active_threads = params->workload.size();
+
+    if (active_threads > Impl::MaxThreads) {
+        panic("Workload Size too large. Increase the 'MaxThreads'"
+              "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
+              "edit your workload size.");
+    }
 #else
     int active_threads = 1;
 #endif
@@ -258,6 +292,8 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
 
     lastRunningCycle = curTick;
 
+    lastActivatedCycle = -1;
+
     contextSwitch = false;
 }
 
@@ -575,31 +611,45 @@ FullO3CPU<Impl>::activateWhenReady(int tid)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::activateContext(int tid, int delay)
+FullO3CPU<Impl>::activateThread(unsigned int tid)
 {
-    // Needs to set each stage to running as well.
     list<unsigned>::iterator isActive = find(
         activeThreads.begin(), activeThreads.end(), tid);
 
     if (isActive == activeThreads.end()) {
-        //May Need to Re-code this if the delay variable is the
-        //delay needed for thread to activate
-        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
+        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
                 tid);
 
         activeThreads.push_back(tid);
     }
+}
+
+
+template <class Impl>
+void
+FullO3CPU<Impl>::activateContext(int tid, int delay)
+{
+    // Needs to set each stage to running as well.
+    if (delay){
+        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
+                "on cycle %d\n", tid, curTick + cycles(delay));
+        scheduleActivateThreadEvent(tid, delay);
+    } else {
+        activateThread(tid);
+    }
 
-    assert(_status == Idle || _status == SwitchedOut);
+    if(lastActivatedCycle < curTick) {
+        scheduleTickEvent(delay);
 
-    scheduleTickEvent(delay);
+        // Be sure to signal that there's some activity so the CPU doesn't
+        // deschedule itself.
+        activityRec.activity();
+        fetch.wakeFromQuiesce();
 
-    // Be sure to signal that there's some activity so the CPU doesn't
-    // deschedule itself.
-    activityRec.activity();
-    fetch.wakeFromQuiesce();
+        lastActivatedCycle = curTick;
 
-    _status = Running;
+        _status = Running;
+    }
 }
 
 template <class Impl>
@@ -1212,4 +1262,4 @@ FullO3CPU<Impl>::updateThreadPriority()
 }
 
 // Forward declaration of FullO3CPU.
-template class FullO3CPU<AlphaSimpleImpl>;
+template class FullO3CPU<O3CPUImpl>;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index b1ebcce9d..1cff6142d 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -49,11 +49,14 @@
 #include "cpu/o3/cpu_policy.hh"
 #include "cpu/o3/scoreboard.hh"
 #include "cpu/o3/thread_state.hh"
+//#include "cpu/o3/thread_context.hh"
 #include "sim/process.hh"
 
 template <class>
 class Checker;
 class ThreadContext;
+template <class>
+class O3ThreadContext;
 class MemObject;
 class Process;
 
@@ -67,6 +70,10 @@ class BaseO3CPU : public BaseCPU
 
     void regStats();
 
+    /** Sets this CPU's ID. */
+    void setCpuId(int id) { cpu_id = id; }
+
+    /** Reads this CPU's ID. */
     int readCpuId() { return cpu_id; }
 
   protected:
@@ -94,6 +101,8 @@ class FullO3CPU : public BaseO3CPU
 
     typedef typename std::list<DynInstPtr>::iterator ListIt;
 
+    friend class O3ThreadContext<Impl>;
+
   public:
     enum Status {
         Running,
@@ -106,6 +115,9 @@ class FullO3CPU : public BaseO3CPU
     /** Overall CPU status. */
     Status _status;
 
+    /** Per-thread status in CPU, used for SMT.  */
+    Status _threadStatus[Impl::MaxThreads];
+
   private:
     class TickEvent : public Event
     {
@@ -142,6 +154,49 @@ class FullO3CPU : public BaseO3CPU
             tickEvent.squash();
     }
 
+    class ActivateThreadEvent : public Event
+    {
+      private:
+        /** Number of Thread to Activate */
+        int tid;
+
+        /** Pointer to the CPU. */
+        FullO3CPU<Impl> *cpu;
+
+      public:
+        /** Constructs the event. */
+        ActivateThreadEvent();
+
+        /** Initialize Event */
+        void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
+
+        /** Processes the event, calling activateThread() on the CPU. */
+        void process();
+
+        /** Returns the description of the event. */
+        const char *description();
+    };
+
+    /** Schedule thread to activate , regardless of its current state. */
+    void scheduleActivateThreadEvent(int tid, int delay)
+    {
+        // Schedule thread to activate, regardless of its current state.
+        if (activateThreadEvent[tid].squashed())
+            activateThreadEvent[tid].reschedule(curTick + cycles(delay));
+        else if (!activateThreadEvent[tid].scheduled())
+            activateThreadEvent[tid].schedule(curTick + cycles(delay));
+    }
+
+    /** Unschedule actiavte thread event, regardless of its current state. */
+    void unscheduleActivateThreadEvent(int tid)
+    {
+        if (activateThreadEvent[tid].scheduled())
+            activateThreadEvent[tid].squash();
+    }
+
+    /** The tick event used for scheduling CPU ticks. */
+    ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
+
   public:
     /** Constructs a CPU with the given parameters. */
     FullO3CPU(Params *params);
@@ -159,6 +214,13 @@ class FullO3CPU : public BaseO3CPU
     /** Initialize the CPU */
     void init();
 
+    /** Returns the Number of Active Threads in the CPU */
+    int numActiveThreads()
+    { return activeThreads.size(); }
+
+    /** Add Thread to Active Threads List */
+    void activateThread(unsigned int tid);
+
     /** Setup CPU to insert a thread's context */
     void insertThread(unsigned tid);
 
@@ -514,6 +576,9 @@ class FullO3CPU : public BaseO3CPU
     /** The cycle that the CPU was last running, used for statistics. */
     Tick lastRunningCycle;
 
+    /** The cycle that the CPU was last activated by a new thread*/
+    Tick lastActivatedCycle;
+
     /** Number of Threads CPU can process */
     unsigned numThreads;
 
diff --git a/src/cpu/o3/decode.cc b/src/cpu/o3/decode.cc
index 4924f018a..896e38331 100644
--- a/src/cpu/o3/decode.cc
+++ b/src/cpu/o3/decode.cc
@@ -28,8 +28,7 @@
  * Authors: Kevin Lim
  */
 
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/decode_impl.hh"
 
-template class DefaultDecode<AlphaSimpleImpl>;
+template class DefaultDecode<O3CPUImpl>;
diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc
index 5f52d0fca..d809b07e4 100644
--- a/src/cpu/o3/fetch.cc
+++ b/src/cpu/o3/fetch.cc
@@ -28,8 +28,7 @@
  * Authors: Kevin Lim
  */
 
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/fetch_impl.hh"
 
-template class DefaultFetch<AlphaSimpleImpl>;
+template class DefaultFetch<O3CPUImpl>;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index e570dbb18..60eb76d17 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -114,8 +114,6 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
     if (numThreads > Impl::MaxThreads)
         fatal("numThreads is not a valid value\n");
 
-    DPRINTF(Fetch, "Fetch constructor called\n");
-
     // Set fetch stage's status to inactive.
     _status = Inactive;
 
@@ -128,6 +126,8 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
     // Figure out fetch policy
     if (policy == "singlethread") {
         fetchPolicy = SingleThread;
+        if (numThreads > 1)
+            panic("Invalid Fetch Policy for a SMT workload.");
     } else if (policy == "roundrobin") {
         fetchPolicy = RoundRobin;
         DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
@@ -559,7 +559,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
             return false;
         }
 
-        DPRINTF(Fetch, "Doing cache access.\n");
+        DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
 
         lastIcacheStall[tid] = curTick;
 
@@ -724,12 +724,15 @@ DefaultFetch<Impl>::tick()
     // Reset the number of the instruction we're fetching.
     numInst = 0;
 
+#if FULL_SYSTEM
     if (fromCommit->commitInfo[0].interruptPending) {
         interruptPending = true;
     }
+
     if (fromCommit->commitInfo[0].clearInterrupt) {
         interruptPending = false;
     }
+#endif
 
     for (threadFetched = 0; threadFetched < numFetchingThreads;
          threadFetched++) {
@@ -903,6 +906,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
         return;
     }
 
+    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
+
     // The current PC.
     Addr &fetch_PC = PC[tid];
 
@@ -1279,6 +1284,6 @@ int
 DefaultFetch<Impl>::branchCount()
 {
     list<unsigned>::iterator threads = (*activeThreads).begin();
-    warn("Branch Count Fetch policy unimplemented\n");
+    panic("Branch Count Fetch policy unimplemented\n");
     return *threads;
 }
diff --git a/src/cpu/o3/iew.cc b/src/cpu/o3/iew.cc
index 8145f4cc7..f99be7fe0 100644
--- a/src/cpu/o3/iew.cc
+++ b/src/cpu/o3/iew.cc
@@ -28,9 +28,8 @@
  * Authors: Kevin Lim
  */
 
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/iew_impl.hh"
 #include "cpu/o3/inst_queue.hh"
 
-template class DefaultIEW<AlphaSimpleImpl>;
+template class DefaultIEW<O3CPUImpl>;
diff --git a/src/cpu/o3/inst_queue.cc b/src/cpu/o3/inst_queue.cc
index f2c6b8213..a539066f9 100644
--- a/src/cpu/o3/inst_queue.cc
+++ b/src/cpu/o3/inst_queue.cc
@@ -28,9 +28,8 @@
  * Authors: Kevin Lim
  */
 
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/inst_queue_impl.hh"
 
 // Force instantiation of InstructionQueue.
-template class InstructionQueue<AlphaSimpleImpl>;
+template class InstructionQueue<O3CPUImpl>;
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index d745faf7b..4c69ca384 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Kevin Lim
+ *          Korey Sewell
  */
 
 #ifndef __CPU_O3_INST_QUEUE_HH__
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 1ef1b2cff..b99bd0900 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Kevin Lim
+ *          Korey Sewell
  */
 
 #include <limits>
@@ -125,7 +126,7 @@ InstructionQueue<Impl>::InstructionQueue(Params *params)
             maxEntries[i] = part_amt;
         }
 
-        DPRINTF(Fetch, "IQ sharing policy set to Partitioned:"
+        DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
                 "%i entries per thread.\n",part_amt);
 
     } else if (policy == "threshold") {
@@ -140,7 +141,7 @@ InstructionQueue<Impl>::InstructionQueue(Params *params)
             maxEntries[i] = thresholdIQ;
         }
 
-        DPRINTF(Fetch, "IQ sharing policy set to Threshold:"
+        DPRINTF(IQ, "IQ sharing policy set to Threshold:"
                 "%i entries per thread.\n",thresholdIQ);
    } else {
        assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
diff --git a/src/cpu/o3/isa_specific.hh b/src/cpu/o3/isa_specific.hh
new file mode 100755
index 000000000..f8a9dd8cc
--- /dev/null
+++ b/src/cpu/o3/isa_specific.hh
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ */
+
+#include "cpu/base.hh"
+
+#if THE_ISA == ALPHA_ISA
+    #include "cpu/o3/alpha/cpu.hh"
+    #include "cpu/o3/alpha/impl.hh"
+    #include "cpu/o3/alpha/params.hh"
+    #include "cpu/o3/alpha/dyn_inst.hh"
+#else
+    #error "O3CPU doesnt support this ISA"
+#endif
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index de0325920..527947281 100644
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -28,11 +28,9 @@
  * Authors: Korey Sewell
  */
 
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_cpu.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/lsq_impl.hh"
 
 // Force the instantiation of LDSTQ for all the implementations we care about.
-template class LSQ<AlphaSimpleImpl>;
+template class LSQ<O3CPUImpl>;
 
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index e935ffa5c..3ca3fa667 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -29,11 +29,9 @@
  *          Korey Sewell
  */
 
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_cpu.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/lsq_unit_impl.hh"
 
 // Force the instantiation of LDSTQ for all the implementations we care about.
-template class LSQUnit<AlphaSimpleImpl>;
+template class LSQUnit<O3CPUImpl>;
 
diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc
index a95103266..6a14dcbff 100644
--- a/src/cpu/o3/mem_dep_unit.cc
+++ b/src/cpu/o3/mem_dep_unit.cc
@@ -28,23 +28,22 @@
  * Authors: Kevin Lim
  */
 
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/store_set.hh"
 #include "cpu/o3/mem_dep_unit_impl.hh"
 
 // Force instantation of memory dependency unit using store sets and
-// AlphaSimpleImpl.
-template class MemDepUnit<StoreSet, AlphaSimpleImpl>;
+// O3CPUImpl.
+template class MemDepUnit<StoreSet, O3CPUImpl>;
 
 #ifdef DEBUG
 template <>
 int
-MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_count = 0;
+MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_count = 0;
 template <>
 int
-MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_insert = 0;
+MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_insert = 0;
 template <>
 int
-MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_erase = 0;
+MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_erase = 0;
 #endif
diff --git a/src/cpu/o3/alpha_params.hh b/src/cpu/o3/params.hh
index f0732733e..69a1bb937 100644..100755
--- a/src/cpu/o3/alpha_params.hh
+++ b/src/cpu/o3/params.hh
@@ -28,47 +28,29 @@
  * Authors: Kevin Lim
  */
 
-#ifndef __CPU_O3_ALPHA_PARAMS_HH__
-#define __CPU_O3_ALPHA_PARAMS_HH__
+#ifndef __CPU_O3_PARAMS_HH__
+#define __CPU_O3_PARAMS_HH__
 
 #include "cpu/o3/cpu.hh"
 
 //Forward declarations
-class AlphaDTB;
-class AlphaITB;
 class FUPool;
-class MemObject;
-class Process;
-class System;
 
 /**
- * This file defines the parameters that will be used for the AlphaO3CPU.
+ * This file defines the parameters that will be used for the O3CPU.
  * This must be defined externally so that the Impl can have a params class
  * defined that it can pass to all of the individual stages.
  */
-
-class AlphaSimpleParams : public BaseO3CPU::Params
+class O3Params : public BaseO3CPU::Params
 {
   public:
-
-#if FULL_SYSTEM
-    AlphaITB *itb; AlphaDTB *dtb;
-#else
-    std::vector<Process *> workload;
-    Process *process;
-#endif // FULL_SYSTEM
-
-    MemObject *mem;
-
-    BaseCPU *checker;
-
     unsigned activity;
 
     //
     // Caches
     //
-//    MemInterface *icacheInterface;
-//    MemInterface *dcacheInterface;
+    //    MemInterface *icacheInterface;
+    //    MemInterface *dcacheInterface;
 
     unsigned cachePorts;
 
diff --git a/src/cpu/o3/rename.cc b/src/cpu/o3/rename.cc
index 9ca8e82c6..443ada0cb 100644
--- a/src/cpu/o3/rename.cc
+++ b/src/cpu/o3/rename.cc
@@ -28,8 +28,7 @@
  * Authors: Kevin Lim
  */
 
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/rename_impl.hh"
 
-template class DefaultRename<AlphaSimpleImpl>;
+template class DefaultRename<O3CPUImpl>;
diff --git a/src/cpu/o3/rob.cc b/src/cpu/o3/rob.cc
index f99e5ccfd..9976049cd 100644
--- a/src/cpu/o3/rob.cc
+++ b/src/cpu/o3/rob.cc
@@ -29,9 +29,8 @@
  *          Nathan Binkert
  */
 
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/rob_impl.hh"
 
 // Force instantiation of InstructionQueue.
-template class ROB<AlphaSimpleImpl>;
+template class ROB<O3CPUImpl>;
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh
index b98d7c4c2..6f8080ef4 100644
--- a/src/cpu/o3/rob.hh
+++ b/src/cpu/o3/rob.hh
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Kevin Lim
+ *          Korey Sewell
  */
 
 #ifndef __CPU_O3_ROB_HH__
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 6277dd68b..d9978b17f 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Kevin Lim
+ *          Korey Sewell
  */
 
 #include "config/full_system.hh"
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
new file mode 100755
index 000000000..d097ee63e
--- /dev/null
+++ b/src/cpu/o3/thread_context.hh
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ *          Korey Sewell
+ */
+
+#ifndef __CPU_O3_THREAD_CONTEXT_HH__
+#define __CPU_O3_THREAD_CONTEXT_HH__
+
+#include "cpu/o3/isa_specific.hh"
+
+class EndQuiesceEvent;
+namespace Kernel {
+    class Statistics;
+};
+
+class TranslatingPort;
+
+/**
+ * Derived ThreadContext class for use with the O3CPU.  It
+ * provides the interface for any external objects to access a
+ * single thread's state and some general CPU state.  Any time
+ * external objects try to update state through this interface,
+ * the CPU will create an event to squash all in-flight
+ * instructions in order to ensure state is maintained correctly.
+ * It must be defined specifically for the O3CPU because
+ * not all architectural state is located within the O3ThreadState
+ * (such as the commit PC, and registers), and specific actions
+ * must be taken when using this interface (such as squashing all
+ * in-flight instructions when doing a write to this interface).
+ */
+template <class Impl>
+class O3ThreadContext : public ThreadContext
+{
+  public:
+    typedef typename Impl::O3CPU O3CPU;
+
+   /** Pointer to the CPU. */
+    O3CPU *cpu;
+
+    /** Pointer to the thread state that this TC corrseponds to. */
+    O3ThreadState<Impl> *thread;
+
+    /** Returns a pointer to this CPU. */
+    virtual BaseCPU *getCpuPtr() { return cpu; }
+
+    /** Sets this CPU's ID. */
+    virtual void setCpuId(int id) { cpu->setCpuId(id); }
+
+    /** Reads this CPU's ID. */
+    virtual int readCpuId() { return cpu->readCpuId(); }
+
+#if FULL_SYSTEM
+    /** Returns a pointer to the system. */
+    virtual System *getSystemPtr() { return cpu->system; }
+
+    /** Returns a pointer to physical memory. */
+    virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
+
+    /** Returns a pointer to this thread's kernel statistics. */
+    virtual Kernel::Statistics *getKernelStats()
+    { return thread->kernelStats; }
+
+    virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+
+    virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL);
+
+    void delVirtPort(VirtualPort *vp);
+#else
+    virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
+
+    /** Returns a pointer to this thread's process. */
+    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
+#endif
+    /** Returns this thread's status. */
+    virtual Status status() const { return thread->status(); }
+
+    /** Sets this thread's status. */
+    virtual void setStatus(Status new_status)
+    { thread->setStatus(new_status); }
+
+    /** Set the status to Active.  Optional delay indicates number of
+     * cycles to wait before beginning execution. */
+    virtual void activate(int delay = 1);
+
+    /** Set the status to Suspended. */
+    virtual void suspend();
+
+    /** Set the status to Unallocated. */
+    virtual void deallocate();
+
+    /** Set the status to Halted. */
+    virtual void halt();
+
+#if FULL_SYSTEM
+    /** Dumps the function profiling information.
+     * @todo: Implement.
+     */
+    virtual void dumpFuncProfile();
+#endif
+    /** Takes over execution of a thread from another CPU. */
+    virtual void takeOverFrom(ThreadContext *old_context);
+
+    /** Registers statistics associated with this TC. */
+    virtual void regStats(const std::string &name);
+
+    /** Serializes state. */
+    virtual void serialize(std::ostream &os);
+    /** Unserializes state. */
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+#if FULL_SYSTEM
+    /** Reads the last tick that this thread was activated on. */
+    virtual Tick readLastActivate();
+    /** Reads the last tick that this thread was suspended on. */
+    virtual Tick readLastSuspend();
+
+    /** Clears the function profiling information. */
+    virtual void profileClear();
+    /** Samples the function profiling information. */
+    virtual void profileSample();
+#endif
+    /** Returns this thread's ID number. */
+    virtual int getThreadNum() { return thread->readTid(); }
+
+    /** Returns the instruction this thread is currently committing.
+     *  Only used when an instruction faults.
+     */
+    virtual TheISA::MachInst getInst();
+
+    /** Copies the architectural registers from another TC into this TC. */
+    virtual void copyArchRegs(ThreadContext *tc);
+
+    /** Resets all architectural registers to 0. */
+    virtual void clearArchRegs();
+
+    /** Reads an integer register. */
+    virtual uint64_t readIntReg(int reg_idx);
+
+    virtual FloatReg readFloatReg(int reg_idx, int width);
+
+    virtual FloatReg readFloatReg(int reg_idx);
+
+    virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
+
+    virtual FloatRegBits readFloatRegBits(int reg_idx);
+
+    /** Sets an integer register to a value. */
+    virtual void setIntReg(int reg_idx, uint64_t val);
+
+    virtual void setFloatReg(int reg_idx, FloatReg val, int width);
+
+    virtual void setFloatReg(int reg_idx, FloatReg val);
+
+    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
+
+    virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
+
+    /** Reads this thread's PC. */
+    virtual uint64_t readPC()
+    { return cpu->readPC(thread->readTid()); }
+
+    /** Sets this thread's PC. */
+    virtual void setPC(uint64_t val);
+
+    /** Reads this thread's next PC. */
+    virtual uint64_t readNextPC()
+    { return cpu->readNextPC(thread->readTid()); }
+
+    /** Sets this thread's next PC. */
+    virtual void setNextPC(uint64_t val);
+
+    /** Reads a miscellaneous register. */
+    virtual MiscReg readMiscReg(int misc_reg)
+    { return cpu->readMiscReg(misc_reg, thread->readTid()); }
+
+    /** Reads a misc. register, including any side-effects the
+     * read might have as defined by the architecture. */
+    virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->readTid()); }
+
+    /** Sets a misc. register. */
+    virtual Fault setMiscReg(int misc_reg, const MiscReg &val);
+
+    /** Sets a misc. register, including any side-effects the
+     * write might have as defined by the architecture. */
+    virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+
+    /** Returns the number of consecutive store conditional failures. */
+    // @todo: Figure out where these store cond failures should go.
+    virtual unsigned readStCondFailures()
+    { return thread->storeCondFailures; }
+
+    /** Sets the number of consecutive store conditional failures. */
+    virtual void setStCondFailures(unsigned sc_failures)
+    { thread->storeCondFailures = sc_failures; }
+
+    // Only really makes sense for old CPU model.  Lots of code
+    // outside the CPU still checks this function, so it will
+    // always return false to keep everything working.
+    /** Checks if the thread is misspeculating.  Because it is
+     * very difficult to determine if the thread is
+     * misspeculating, this is set as false. */
+    virtual bool misspeculating() { return false; }
+
+#if !FULL_SYSTEM
+    /** Gets a syscall argument by index. */
+    virtual IntReg getSyscallArg(int i);
+
+    /** Sets a syscall argument. */
+    virtual void setSyscallArg(int i, IntReg val);
+
+    /** Sets the syscall return value. */
+    virtual void setSyscallReturn(SyscallReturn return_value);
+
+    /** Executes a syscall in SE mode. */
+    virtual void syscall(int64_t callnum)
+    { return cpu->syscall(callnum, thread->readTid()); }
+
+    /** Reads the funcExeInst counter. */
+    virtual Counter readFuncExeInst() { return thread->funcExeInst; }
+#endif
+};
+
+#endif
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
new file mode 100755
index 000000000..cfb71f623
--- /dev/null
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -0,0 +1,489 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ *          Korey Sewell
+ */
+
+#include "cpu/o3/thread_context.hh"
+#include "cpu/quiesce_event.hh"
+
+using namespace TheISA;
+
+#if FULL_SYSTEM
+template <class Impl>
+VirtualPort *
+O3ThreadContext<Impl>::getVirtPort(ThreadContext *src_tc)
+{
+    if (!src_tc)
+        return thread->getVirtPort();
+
+    VirtualPort *vp;
+    Port *mem_port;
+
+    vp = new VirtualPort("tc-vport", src_tc);
+    mem_port = cpu->system->physmem->getPort("functional");
+    mem_port->setPeer(vp);
+    vp->setPeer(mem_port);
+    return vp;
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::dumpFuncProfile()
+{
+    // Currently not supported
+}
+#endif
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
+{
+    // some things should already be set up
+#if FULL_SYSTEM
+    assert(getSystemPtr() == old_context->getSystemPtr());
+#else
+    assert(getProcessPtr() == old_context->getProcessPtr());
+#endif
+
+    // copy over functional state
+    setStatus(old_context->status());
+    copyArchRegs(old_context);
+    setCpuId(old_context->readCpuId());
+
+#if !FULL_SYSTEM
+    thread->funcExeInst = old_context->readFuncExeInst();
+#else
+    EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
+    if (other_quiesce) {
+        // Point the quiesce event's TC at this TC so that it wakes up
+        // the proper CPU.
+        other_quiesce->tc = this;
+    }
+    if (thread->quiesceEvent) {
+        thread->quiesceEvent->tc = this;
+    }
+
+    // Transfer kernel stats from one CPU to the other.
+    thread->kernelStats = old_context->getKernelStats();
+//    storeCondFailures = 0;
+    cpu->lockFlag = false;
+#endif
+
+    old_context->setStatus(ThreadContext::Unallocated);
+
+    thread->inSyscall = false;
+    thread->trapPending = false;
+}
+
+#if FULL_SYSTEM
+template <class Impl>
+void
+O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp)
+{
+    delete vp->getPeer();
+    delete vp;
+}
+#endif
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::activate(int delay)
+{
+    DPRINTF(O3CPU, "Calling activate on AlphaTC\n");
+
+    if (thread->status() == ThreadContext::Active)
+        return;
+
+#if FULL_SYSTEM
+    thread->lastActivate = curTick;
+#endif
+
+    if (thread->status() == ThreadContext::Unallocated) {
+        cpu->activateWhenReady(thread->readTid());
+        return;
+    }
+
+    thread->setStatus(ThreadContext::Active);
+
+    // status() == Suspended
+    cpu->activateContext(thread->readTid(), delay);
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::suspend()
+{
+    DPRINTF(O3CPU, "Calling suspend on AlphaTC\n");
+
+    if (thread->status() == ThreadContext::Suspended)
+        return;
+
+#if FULL_SYSTEM
+    thread->lastActivate = curTick;
+    thread->lastSuspend = curTick;
+#endif
+/*
+#if FULL_SYSTEM
+    // Don't change the status from active if there are pending interrupts
+    if (cpu->check_interrupts()) {
+        assert(status() == ThreadContext::Active);
+        return;
+    }
+#endif
+*/
+    thread->setStatus(ThreadContext::Suspended);
+    cpu->suspendContext(thread->readTid());
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::deallocate()
+{
+    DPRINTF(O3CPU, "Calling deallocate on AlphaTC\n");
+
+    if (thread->status() == ThreadContext::Unallocated)
+        return;
+
+    thread->setStatus(ThreadContext::Unallocated);
+    cpu->deallocateContext(thread->readTid());
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::halt()
+{
+    DPRINTF(O3CPU, "Calling halt on AlphaTC\n");
+
+    if (thread->status() == ThreadContext::Halted)
+        return;
+
+    thread->setStatus(ThreadContext::Halted);
+    cpu->haltContext(thread->readTid());
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::regStats(const std::string &name)
+{
+#if FULL_SYSTEM
+    thread->kernelStats = new Kernel::Statistics(cpu->system);
+    thread->kernelStats->regStats(name + ".kern");
+#endif
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::serialize(std::ostream &os)
+{
+#if FULL_SYSTEM
+    if (thread->kernelStats)
+        thread->kernelStats->serialize(os);
+#endif
+
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string &section)
+{
+#if FULL_SYSTEM
+    if (thread->kernelStats)
+        thread->kernelStats->unserialize(cp, section);
+#endif
+
+}
+
+#if FULL_SYSTEM
+template <class Impl>
+Tick
+O3ThreadContext<Impl>::readLastActivate()
+{
+    return thread->lastActivate;
+}
+
+template <class Impl>
+Tick
+O3ThreadContext<Impl>::readLastSuspend()
+{
+    return thread->lastSuspend;
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::profileClear()
+{}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::profileSample()
+{}
+#endif
+
+template <class Impl>
+TheISA::MachInst
+O3ThreadContext<Impl>:: getInst()
+{
+    return thread->getInst();
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
+{
+    // This function will mess things up unless the ROB is empty and
+    // there are no instructions in the pipeline.
+    unsigned tid = thread->readTid();
+    PhysRegIndex renamed_reg;
+
+    // First loop through the integer registers.
+    for (int i = 0; i < TheISA::NumIntRegs; ++i) {
+        renamed_reg = cpu->renameMap[tid].lookup(i);
+
+        DPRINTF(O3CPU, "Copying over register %i, had data %lli, "
+                "now has data %lli.\n",
+                renamed_reg, cpu->readIntReg(renamed_reg),
+                tc->readIntReg(i));
+
+        cpu->setIntReg(renamed_reg, tc->readIntReg(i));
+    }
+
+    // Then loop through the floating point registers.
+    for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
+        renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag);
+        cpu->setFloatRegBits(renamed_reg,
+                             tc->readFloatRegBits(i));
+    }
+
+    // Copy the misc regs.
+    copyMiscRegs(tc, this);
+
+    // Then finally set the PC and the next PC.
+    cpu->setPC(tc->readPC(), tid);
+    cpu->setNextPC(tc->readNextPC(), tid);
+#if !FULL_SYSTEM
+    this->thread->funcExeInst = tc->readFuncExeInst();
+#endif
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::clearArchRegs()
+{}
+
+template <class Impl>
+uint64_t
+O3ThreadContext<Impl>::readIntReg(int reg_idx)
+{
+    return cpu->readArchIntReg(reg_idx, thread->readTid());
+}
+
+template <class Impl>
+FloatReg
+O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
+{
+    switch(width) {
+      case 32:
+        return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
+      case 64:
+        return cpu->readArchFloatRegDouble(reg_idx, thread->readTid());
+      default:
+        panic("Unsupported width!");
+        return 0;
+    }
+}
+
+template <class Impl>
+FloatReg
+O3ThreadContext<Impl>::readFloatReg(int reg_idx)
+{
+    return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
+}
+
+template <class Impl>
+FloatRegBits
+O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
+{
+    DPRINTF(Fault, "Reading floatint register through the TC!\n");
+    return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
+}
+
+template <class Impl>
+FloatRegBits
+O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
+{
+    return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
+{
+    cpu->setArchIntReg(reg_idx, val, thread->readTid());
+
+    // Squash if we're not already in a state update mode.
+    if (!thread->trapPending && !thread->inSyscall) {
+        cpu->squashFromTC(thread->readTid());
+    }
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
+{
+    switch(width) {
+      case 32:
+        cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
+        break;
+      case 64:
+        cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid());
+        break;
+    }
+
+    // Squash if we're not already in a state update mode.
+    if (!thread->trapPending && !thread->inSyscall) {
+        cpu->squashFromTC(thread->readTid());
+    }
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
+{
+    cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
+
+    if (!thread->trapPending && !thread->inSyscall) {
+        cpu->squashFromTC(thread->readTid());
+    }
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
+                                             int width)
+{
+    DPRINTF(Fault, "Setting floatint register through the TC!\n");
+    cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
+
+    // Squash if we're not already in a state update mode.
+    if (!thread->trapPending && !thread->inSyscall) {
+        cpu->squashFromTC(thread->readTid());
+    }
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
+{
+    cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
+
+    // Squash if we're not already in a state update mode.
+    if (!thread->trapPending && !thread->inSyscall) {
+        cpu->squashFromTC(thread->readTid());
+    }
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setPC(uint64_t val)
+{
+    cpu->setPC(val, thread->readTid());
+
+    // Squash if we're not already in a state update mode.
+    if (!thread->trapPending && !thread->inSyscall) {
+        cpu->squashFromTC(thread->readTid());
+    }
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setNextPC(uint64_t val)
+{
+    cpu->setNextPC(val, thread->readTid());
+
+    // Squash if we're not already in a state update mode.
+    if (!thread->trapPending && !thread->inSyscall) {
+        cpu->squashFromTC(thread->readTid());
+    }
+}
+
+template <class Impl>
+Fault
+O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
+{
+    Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid());
+
+    // Squash if we're not already in a state update mode.
+    if (!thread->trapPending && !thread->inSyscall) {
+        cpu->squashFromTC(thread->readTid());
+    }
+
+    return ret_fault;
+}
+
+template <class Impl>
+Fault
+O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg,
+                                                const MiscReg &val)
+{
+    Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val,
+                                                thread->readTid());
+
+    // Squash if we're not already in a state update mode.
+    if (!thread->trapPending && !thread->inSyscall) {
+        cpu->squashFromTC(thread->readTid());
+    }
+
+    return ret_fault;
+}
+
+#if !FULL_SYSTEM
+
+template <class Impl>
+TheISA::IntReg
+O3ThreadContext<Impl>::getSyscallArg(int i)
+{
+    return cpu->getSyscallArg(i, thread->readTid());
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setSyscallArg(int i, IntReg val)
+{
+    cpu->setSyscallArg(i, val, thread->readTid());
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value)
+{
+    cpu->setSyscallReturn(return_value, thread->readTid());
+}
+
+#endif // FULL_SYSTEM
+