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authorKevin Lim <ktlim@umich.edu>2006-07-13 13:09:29 -0400
committerKevin Lim <ktlim@umich.edu>2006-07-13 13:09:29 -0400
commit2af213022ce6d58eee2809f300d7450e89a4bce9 (patch)
tree304393e05611feffdcd18707384942b55e6a7764 /src/cpu/o3
parenta0a952d5ff8e27d34c7fa68fe5199c57670c53d1 (diff)
downloadgem5-2af213022ce6d58eee2809f300d7450e89a4bce9.tar.xz
Fix for bug when squashing and the fetching. Now fetch checks if the cache data is valid.
--HG-- extra : convert_revision : 07b8eda3e90bbbb3ed470c8cc3cf1b63371ab529
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/fetch.hh3
-rw-r--r--src/cpu/o3/fetch_impl.hh8
2 files changed, 9 insertions, 2 deletions
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 0331cf07f..931919af8 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -407,6 +407,9 @@ class DefaultFetch
/** The PC of the cacheline that has been loaded. */
Addr cacheDataPC[Impl::MaxThreads];
+ /** Whether or not the cache data is valid. */
+ bool cacheDataValid[Impl::MaxThreads];
+
/** Size of instructions. */
int instSize;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 4045492ca..4184e1867 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -162,6 +162,8 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
// Create space to store a cache line.
cacheData[tid] = new uint8_t[cacheBlkSize];
+ cacheDataPC[tid] = 0;
+ cacheDataValid[tid] = false;
stalls[tid].decode = 0;
stalls[tid].rename = 0;
@@ -358,6 +360,7 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
}
memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
+ cacheDataValid[tid] = true;
if (!drainPending) {
// Wake up the CPU (if it went to sleep and was waiting on
@@ -520,7 +523,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
fetch_PC = icacheBlockAlignPC(fetch_PC);
// If we've already got the block, no need to try to fetch it again.
- if (fetch_PC == cacheDataPC[tid]) {
+ if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) {
return true;
}
@@ -555,9 +558,10 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
// Build packet here.
PacketPtr data_pkt = new Packet(mem_req,
Packet::ReadReq, Packet::Broadcast);
- data_pkt->dataDynamic(new uint8_t[cacheBlkSize]);
+ data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
cacheDataPC[tid] = fetch_PC;
+ cacheDataValid[tid] = false;
DPRINTF(Fetch, "Fetch: Doing instruction read.\n");